Samsung 3.5" hard disk drives DMACK- DMA Acknowledge, Dmarq DMA Request, Intrq Drive Interrupt

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DISK DRIVE OPERATION

6.2.3.8DMACK- (DMA Acknowledge)

This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available.

6.2.3.9DMARQ (DMA Request)

This signal, used for DMA data transfers between host and drive, shall be asserted by the drive when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR- and DIOW-. The signal is used in handshake manner with DMACK- (i.e., the drive shall wait until the host asserts DMACK- before negating DMARQ and re-asserting DMARQ if there is more data to transfer).

When a DMA operation is enabled, IOCS16- and CSIFX- shall not be asserted and transfers shall be 16-bits wide.

6.2.3.10INTRQ (Drive Interrupt)

This signal is used to interrupt the host system. INTRQ is asserted only when the drive has a pending interrupt, the drive is selected, and the host has cleared nIEN in the Device Control register. If nIEN=1, or the drive is not selected, this output is in a high impedance state, regardless of the presence or absence of a pending interrupt.

INTRQ is negated by:

•Assertion of RESET- or

•The setting of SRST of the Device Control register, or

•The host writing to the Command register, or

•The host reading from the Status register.

On PIO transfers, INTRQ is asserted at the beginning of each data block to be transferred. A data block is typically a single sector, except when declared otherwise by use of the Set Multiple command. An exception occurs on Format Track, Write Sector(s), Write Buffer, and Write Long commands: INTRQ shall not be asserted at the beginning of the first data block to be transferred.

6.2.3.11IOCS16- (Drive 16-bit I/O)

IOCS16- indicates to the host system that the 16-bit data port has been addressed and that the drive is ready to send or receive a 16-bit word. This is an open collector output.

•When transferring in PIO mode, if IOCS16- is not asserted, DD0-7 is used for 8-bit transfers.

•When transferring in PIO mode, if IOCS16- is asserted, DD0-15 is used for 16-bit data transfers.

SpinPoint V40 Product Manual

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Irmware F Eatures Ervo S Ystem EAD and W Rite O PerationsSmart Protocol Overview Programming RequirementsTiming Service and Repair Maintenance Precautions107 General InformationTable of Figures Page Manual Organization User DefinitionScope Terminology and Conventions Commands and MessagesComputer Message Format C/SReference Introduction Key FeaturesDescription Hardware Requirements Standards and RegulationsSpecifications Specification SummaryLogical Configurations Physical SpecificationsPerformance Specifications 28.71 Power RequirementsSV6003H SV6014H SV8004H Environmental SpecificationsMtbf POH Reliability SpecificationsSpace Requirements InstallationMounting Unpacking InstructionsOrientation 2Mounting Dimensions in Millimeters 3Mounting-Screw Clearance ClearanceDC Power Connector Cable ConnectorsAT-Bus Interface Connector VentilationSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration 7DC Power Connector and AT-Bus Interface Cable Connections Drive InstallationParameter System Startup ProcedureSystem Setup Base Casting Assembly Head / Disk Assembly HDADC Spindle Motor Assembly Disk Drive OperationExploded Mechanical View Head Stack Assembly Disk Stack AssemblyVoice Coil Motor and Actuator Latch Assemblies Air Filtration SystemDrive Electronics Digital Signal Process and Interface ControllerAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Disk Control Block Buffer Control BlockSpinPoint V40 Product Manual Read/Write IC Power ManagementDisk ECC Control Block Frequency SynthesizerAutomatic Gain Control Time Base GeneratorAsymmetry Correction Circuitry ASC Analog Anti-Aliasing Low Pass Filter3Read/Write 88C5200 Read and Write Operations Servo SystemRead Channel Write Channel Firmware FeaturesRead Caching Write Caching Automatic Defect Allocation Defect ManagementMulti-burst ECC Correction SmartBlank Signal Summary Signal ConventionsPhysical Interface Signal Descriptions Dmarq DMA Request DMACK- DMA AcknowledgeIntrq Drive Interrupt IOCS16- Drive 16-bit I/ORESET- Drive Reset PDIAG- Passed DiagnosticsIordy I/O Channel Ready SD4 SD8 SD6 SD9 SD5SD3 SD2Drive Host DriveDIR General Logical InterfaceBit Conventions EnvironmentSpinPoint V40 Product Manual 2 I/O Register Address Command Block RegistersControl Block Registers N N N A a aAlternate Status Register 3F6h Control Block Register DescriptionsDrive Address Register 3F7h Device Control Register 3F6hFeatures Register 1F1h Command Block Register DescriptionsError Register 1F1h Data Register 1F0hSector Count Register 1F2h Command Register 1F7hCylinder High Register 1F5h Cylinder Low Register 1F4hBSY Drdy DWF DSC DRQ Corr IDX ERR Status Register 1F7hAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Execute Device Diagnostics 90h Check Power Mode 98h, E5hDownload Micro Code 92h Format Track 50h Flush Cache E7hIdentify Device ECh Xxxx Word Content DescriptionCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle Immediate 95h,E1h Idle 97h,E3hInitialize Device Parameters 91h Read Long 22hwith retry, 23h without retry Read Buffer E4hRead Multiple Command C4h Read Sectors 20hwith retry, 21hwithout retry Read Native Max Address F8hRecalibrate 1xh Read Verify Sectors 40hwith retry, 41hwithout retrySeek 7xh Mode Set Features EFhLBA InputsNormal outputs BSY Drdy DRQ ERRDescription Sleep 99h, E6h Set Multiple Mode C6hStandby 96h,E2h Smart disable operation D9hSmart B0h Smart enable operations D8h Smart enable/disable attribute autosave D2hSmart execute off-line immediate D4h Byte Descriptions Smart read data D0hOff-line data collection capability Value DefinitionSmart read log sector D5h Smart capabilitySmart return status DAh Smart save attribution value D3hStandby Immediate 94h, E0h Standby 96h, E2hWrite Buffer E8h Write DMA CAhWrite Sectors 30hwith retry, 31hwithout retry Write Multiple Command C5hSpinPoint V40 Product Manual Error Posting Reset ResponseProgramming Requirements BBK Command Error Register Status RegisterSleep mode Power ConditionsStandby mode Idle modeNormal mode Protocol Overview PIO Data in CommandsPIO Read Command PIO Data Out CommandsPIO Read Aborted Command PIO Write Aborted Command PIO Write CommandBSY=0 DRDY=1 BSY=1 BSY=0 DRQ=1 BSY=1 DRQ=0Non-Data Commands DMA Data Transfer Commands BSY=0 BSY=1 Aborted DMA Command Initialize DMA Reset DMA StatusBSY=1 BSY=0 Register transfers TimingDIOR-/DIOW Write PIO data transfers PIO timing parameters ModeAddr valid See note T1 t2 DIOR-/DIOW DIOR-/DIOW Multiword DMA data transferMultiword DMA timing parameters Mode Initiating an Ultra DMA data in burst Ultra DMA data transfer19Ultra DMA data burst timing requirements Ultra DMA data burst timing requirements5Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst6Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst7Device terminating an Ultra DMA data in burst 100 Device terminating an Ultra DMA data in burst8Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst9Initiating an Ultra DMA data out burst 102 Initiating an Ultra DMA data out burst10Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst11Device pausing an Ultra DMA data out burst 104 Device pausing an Ultra DMA data out burst12Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst13Device terminating an Ultra DMA data out burst 106 Device terminating an Ultra DMA data out burstService And Repair Maintenance PrecautionsGeneral Information
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