Samsung spinpoint v40, 3.5" hard disk drives manual Time Base Generator, Automatic Gain Control

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DISK DRIVE OPERATION

The read/write channel functions include a time base generator, AGC circuitry, asymmetry correction circuitry (ASC), analog anti-aliasing low-pass filter, analog to digital converter (ADC), digital FIR filter, timing recovery circuits, Viterbi detector, sync mark detection, 32/34 rate block code ENDEC, serializer and de-serializer, and write pre-compensation circuits. Servo functions include servo data detection and PES demodulation. Additionally the 88C5200 contains specialized circuitry to perform various parametric measurements on the processed read signal. This allows for implementation of self-tuning and optimization capability in every drive built using the 88C5200.

A 9-bit NRZ interface is provided to support high speed data transfers to and from the controller. Programming of the 88C5200 is performed through a serial interface. The serial interface is also used to read various channel parameters that are computed on the fly.

5.2.3.1Time Base Generator

The time base generator provides the write frequency and serves as a reference clock to the synchronizer during non-read mode.

5.2.3.2Automatic Gain Control

The AGC accepts a differential signal from the pre-amp, and provide a constant output amplitude to the analog filter. It’s capable of accepting signal ranges from 40 mV to 400 mVppd.

5.2.3.3Asymmetry Correction Circuitry (ASC)

The ASC circuit is designed to correct for amplitude asymmetry introduced by MR heads. The compensation range of this circuit is +/-45%. This circuit allows optimal bias current to be used independent of the asymmetry effect.

5.2.3.4Analog Anti-Aliasing Low Pass Filter

The 7th order equal-ripple analog filter provide filtering of the analog signal from AGC before it’s being converted to digital signal with the ADC. It’s main function is to avoid aliasing for the ADC circuit.

5.2.3.5Analog to Digital Converter (ADC) and FIR

The output of the analog filter is quantified using a 6 bit FLASH ADC. The digitized data is then equalized by the FIR to the NPV target response for Viterbi detection. The FIR filter consists of 7 independent programmable taps.

32	SpinPoint V40 Product Manual

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Irmware F Eatures Ervo S Ystem EAD and W Rite O PerationsSmart Protocol Overview Programming RequirementsTiming Maintenance Precautions Service and Repair107 General InformationTable of Figures Page Manual Organization User DefinitionScope Commands and Messages Terminology and ConventionsComputer Message Format C/SReference Introduction Key FeaturesDescription Standards and Regulations Hardware RequirementsSpecification Summary SpecificationsPhysical Specifications Logical ConfigurationsPerformance Specifications Power Requirements 28.71Environmental Specifications SV6003H SV6014H SV8004HReliability Specifications Mtbf POHInstallation Space RequirementsMounting Unpacking InstructionsOrientation 2Mounting Dimensions in Millimeters Clearance 3Mounting-Screw ClearanceCable Connectors DC Power ConnectorAT-Bus Interface Connector VentilationSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration Drive Installation 7DC Power Connector and AT-Bus Interface Cable ConnectionsSystem Startup Procedure ParameterSystem Setup Head / Disk Assembly HDA Base Casting AssemblyDC Spindle Motor Assembly Disk Drive OperationExploded Mechanical View Disk Stack Assembly Head Stack AssemblyVoice Coil Motor and Actuator Latch Assemblies Air Filtration SystemDrive Electronics Digital Signal Process and Interface ControllerAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Buffer Control Block Disk Control BlockSpinPoint V40 Product Manual Power Management Read/Write ICDisk ECC Control Block Frequency SynthesizerTime Base Generator Automatic Gain ControlAsymmetry Correction Circuitry ASC Analog Anti-Aliasing Low Pass Filter3Read/Write 88C5200 Read and Write Operations Servo SystemRead Channel Write Channel Firmware FeaturesRead Caching Write Caching Defect Management Automatic Defect AllocationMulti-burst ECC Correction SmartBlank Signal Summary Signal ConventionsPhysical Interface Signal Descriptions DMACK- DMA Acknowledge Dmarq DMA RequestIntrq Drive Interrupt IOCS16- Drive 16-bit I/ORESET- Drive Reset PDIAG- Passed DiagnosticsIordy I/O Channel Ready SD8 SD6 SD9 SD5 SD4SD3 SD2Drive Drive HostDIR Logical Interface GeneralBit Conventions EnvironmentSpinPoint V40 Product Manual Command Block Registers 2 I/O Register AddressControl Block Registers N N N A a aControl Block Register Descriptions Alternate Status Register 3F6hDrive Address Register 3F7h Device Control Register 3F6hCommand Block Register Descriptions Features Register 1F1hError Register 1F1h Data Register 1F0hCommand Register 1F7h Sector Count Register 1F2hCylinder High Register 1F5h Cylinder Low Register 1F4hStatus Register 1F7h BSY Drdy DWF DSC DRQ Corr IDX ERRAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Execute Device Diagnostics 90h Check Power Mode 98h, E5hDownload Micro Code 92h Format Track 50h Flush Cache E7hIdentify Device ECh Word Content Description XxxxCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle Immediate 95h,E1h Idle 97h,E3hInitialize Device Parameters 91h Read Buffer E4h Read Long 22hwith retry, 23h without retryRead Multiple Command C4h Read Native Max Address F8h Read Sectors 20hwith retry, 21hwithout retryRecalibrate 1xh Read Verify Sectors 40hwith retry, 41hwithout retrySeek 7xh Set Features EFh ModeInputs LBANormal outputs BSY Drdy DRQ ERRDescription Set Multiple Mode C6h Sleep 99h, E6hStandby 96h,E2h Smart disable operation D9hSmart B0h Smart enable operations D8h Smart enable/disable attribute autosave D2hSmart execute off-line immediate D4h Smart read data D0h Byte DescriptionsValue Definition Off-line data collection capabilitySmart capability Smart read log sector D5hSmart return status DAh Smart save attribution value D3hStandby 96h, E2h Standby Immediate 94h, E0hWrite Buffer E8h Write DMA CAhWrite Multiple Command C5h Write Sectors 30hwith retry, 31hwithout retrySpinPoint V40 Product Manual Error Posting Reset ResponseProgramming Requirements Command Error Register Status Register BBKPower Conditions Sleep modeStandby mode Idle modeNormal mode PIO Data in Commands Protocol OverviewPIO Read Command PIO Data Out CommandsPIO Read Aborted Command PIO Write Command PIO Write Aborted CommandBSY=0 DRDY=1 BSY=1 BSY=0 DRQ=1 BSY=1 DRQ=0Non-Data Commands DMA Data Transfer Commands BSY=0 BSY=1 Aborted DMA Command Initialize DMA Reset DMA StatusBSY=1 BSY=0 Timing Register transfersDIOR-/DIOW Write PIO timing parameters Mode PIO data transfersAddr valid See note T1 t2 DIOR-/DIOW Multiword DMA data transfer DIOR-/DIOWMultiword DMA timing parameters Mode Ultra DMA data transfer Initiating an Ultra DMA data in burstUltra DMA data burst timing requirements 19Ultra DMA data burst timing requirementsSustained Ultra DMA data in burst 5Sustained Ultra DMA data in burstHost pausing an Ultra DMA data in burst 6Host pausing an Ultra DMA data in burstDevice terminating an Ultra DMA data in burst 7Device terminating an Ultra DMA data in burst 100Host terminating an Ultra DMA data in burst 8Host terminating an Ultra DMA data in burstInitiating an Ultra DMA data out burst 9Initiating an Ultra DMA data out burst 102Sustained Ultra DMA data out burst 10Sustained Ultra DMA data out burstDevice pausing an Ultra DMA data out burst 11Device pausing an Ultra DMA data out burst 104Host terminating an Ultra DMA data out burst 12Host terminating an Ultra DMA data out burstDevice terminating an Ultra DMA data out burst 13Device terminating an Ultra DMA data out burst 106Service And Repair Maintenance PrecautionsGeneral Information