Samsung spinpoint v40 manual Logical Interface, General, Bit Conventions, Environment

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DISK DRIVE OPERATION

6.3Logical Interface

6.3.1General

6.3.1.1Bit Conventions

Bit names are shown in all upper case letters except where a lower case n precedes a bit name. This indicates that when nBIT=0 (bit is zero) the action is true, and when nBIT=1 (bit is one) the action is false. If there is no proceeding n, then when BIT=1 it is true, and when BIT=0 it is false.

A bit can be set to one or cleared to zero, and polarity influences whether it is to be interpreted as true or false:

True BIT=1 nBIT=0

False BIT=0 nBIT=1

6.3.1.2Environment

Data is transferred in parallel (16 bits) either to or from host memory to the device’s buffer under the direction of commands previously transferred from the host. The device performs all of the operations necessary to properly write data to, or read data from, the media. Data read from the media is stored in the device’s buffer pending transfer to the host memory, and data is transferred from the host memory to the device’s buffer to be written to the media.

The devices using this interface shall be programmed by the host computer to perform commands and return status to the host at command completion. When two devices are daisy chained on the interface, commands are written in parallel to both devices, and for all except the Execute Diagnostics command, only the selected device executes the command. On an Execute Diagnostics command addressed to Device 0, both devices shall execute the command, and Device 1 shall post its status to Device 0 via PDIAG-.

Drives are selected by the DEV bit in the Drive/Head register (see 6.3.4.9), and by a jumper or switch on the device designating it as either Device 0 or Device 1. When DEV=0, Device 0 is selected. When DEV=1, Device 1 is selected. When a single device is attached to the interface, it shall be set as Device 0.

Throughout this document, device selection always refers to the state of the DEV bit, the position of the Device 0/Device 1 jumper or switch, or use of the CSEL pin.

A device can operate in either of two addressing modes, CHS or LBA, on a command-by-command basis. A device, which can support LBA mode, is indicated in the register, Sector Number register, Cylinder Low mode in the Device/Head register, Sector Number register, Cylinder Low register, Cylinder High register and HS3-HS0 of the Device/Head register contains the zero based-LBA.

This term defines the addressing mode of the device as being by physical sector address. The physical sector address is made up of three fields: the sector number, the head number and the cylinder number. Sectors are numbered from 1 to a device specific maximum value, which cannot exceed 255. Heads are numbered from 0 to a device specific maximum value, which cannot exceed 15. Cylinders are numbered from 0 to a device specific maximum value, which cannot exceed 65,535. Typically, sequential access to the media is accomplished by treating the sector number as the least significant portion, the head number as the mid portion, and the cylinder number as the most significant portion of the CHS address.

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SpinPoint V40 Product Manual

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Ervo S Ystem EAD and W Rite O Perations Irmware F EaturesSmart Programming Requirements Protocol OverviewTiming 107 Maintenance PrecautionsService and Repair General InformationTable of Figures Page User Definition Manual OrganizationScope Computer Message Commands and MessagesTerminology and Conventions Format C/SReference Key Features IntroductionDescription Standards and Regulations Hardware RequirementsSpecification Summary SpecificationsPhysical Specifications Logical ConfigurationsPerformance Specifications Power Requirements 28.71Environmental Specifications SV6003H SV6014H SV8004HReliability Specifications Mtbf POHInstallation Space RequirementsUnpacking Instructions MountingOrientation 2Mounting Dimensions in Millimeters Clearance 3Mounting-Screw ClearanceAT-Bus Interface Connector Cable ConnectorsDC Power Connector VentilationSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration Drive Installation 7DC Power Connector and AT-Bus Interface Cable ConnectionsSystem Startup Procedure ParameterSystem Setup DC Spindle Motor Assembly Head / Disk Assembly HDABase Casting Assembly Disk Drive OperationExploded Mechanical View Voice Coil Motor and Actuator Latch Assemblies Disk Stack AssemblyHead Stack Assembly Air Filtration SystemDigital Signal Process and Interface Controller Drive ElectronicsAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Buffer Control Block Disk Control BlockSpinPoint V40 Product Manual Disk ECC Control Block Power ManagementRead/Write IC Frequency SynthesizerAsymmetry Correction Circuitry ASC Time Base GeneratorAutomatic Gain Control Analog Anti-Aliasing Low Pass Filter3Read/Write 88C5200 Servo System Read and Write OperationsRead Channel Firmware Features Write ChannelRead Caching Write Caching Multi-burst ECC Correction Defect ManagementAutomatic Defect Allocation SmartBlank Signal Conventions Signal SummaryPhysical Interface Signal Descriptions Intrq Drive Interrupt DMACK- DMA AcknowledgeDmarq DMA Request IOCS16- Drive 16-bit I/OPDIAG- Passed Diagnostics RESET- Drive ResetIordy I/O Channel Ready SD3 SD8 SD6 SD9 SD5SD4 SD2Drive Drive HostDIR Bit Conventions Logical InterfaceGeneral EnvironmentSpinPoint V40 Product Manual Control Block Registers Command Block Registers2 I/O Register Address N N N A a aDrive Address Register 3F7h Control Block Register DescriptionsAlternate Status Register 3F6h Device Control Register 3F6hError Register 1F1h Command Block Register DescriptionsFeatures Register 1F1h Data Register 1F0hCylinder High Register 1F5h Command Register 1F7hSector Count Register 1F2h Cylinder Low Register 1F4hStatus Register 1F7h BSY Drdy DWF DSC DRQ Corr IDX ERRAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Check Power Mode 98h, E5h Execute Device Diagnostics 90hDownload Micro Code 92h Flush Cache E7h Format Track 50hIdentify Device ECh Word Content Description XxxxCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle 97h,E3h Idle Immediate 95h,E1hInitialize Device Parameters 91h Read Buffer E4h Read Long 22hwith retry, 23h without retryRead Multiple Command C4h Read Native Max Address F8h Read Sectors 20hwith retry, 21hwithout retryRead Verify Sectors 40hwith retry, 41hwithout retry Recalibrate 1xhSeek 7xh Set Features EFh ModeNormal outputs InputsLBA BSY Drdy DRQ ERRDescription Set Multiple Mode C6h Sleep 99h, E6hSmart disable operation D9h Standby 96h,E2hSmart B0h Smart enable/disable attribute autosave D2h Smart enable operations D8hSmart execute off-line immediate D4h Smart read data D0h Byte DescriptionsValue Definition Off-line data collection capabilitySmart return status DAh Smart capabilitySmart read log sector D5h Smart save attribution value D3hWrite Buffer E8h Standby 96h, E2hStandby Immediate 94h, E0h Write DMA CAhWrite Multiple Command C5h Write Sectors 30hwith retry, 31hwithout retrySpinPoint V40 Product Manual Reset Response Error PostingProgramming Requirements Command Error Register Status Register BBKStandby mode Power ConditionsSleep mode Idle modeNormal mode PIO Data in Commands Protocol OverviewPIO Data Out Commands PIO Read CommandPIO Read Aborted Command BSY=0 DRDY=1 BSY=1 PIO Write CommandPIO Write Aborted Command BSY=0 DRQ=1 BSY=1 DRQ=0Non-Data Commands DMA Data Transfer Commands Aborted DMA Command Initialize DMA Reset DMA Status BSY=0 BSY=1BSY=1 BSY=0 Timing Register transfersDIOR-/DIOW Write PIO timing parameters Mode PIO data transfersAddr valid See note T1 t2 DIOR-/DIOW Multiword DMA data transfer DIOR-/DIOWMultiword DMA timing parameters Mode Ultra DMA data transfer Initiating an Ultra DMA data in burstUltra DMA data burst timing requirements 19Ultra DMA data burst timing requirementsSustained Ultra DMA data in burst 5Sustained Ultra DMA data in burstHost pausing an Ultra DMA data in burst 6Host pausing an Ultra DMA data in burstDevice terminating an Ultra DMA data in burst 7Device terminating an Ultra DMA data in burst 100Host terminating an Ultra DMA data in burst 8Host terminating an Ultra DMA data in burstInitiating an Ultra DMA data out burst 9Initiating an Ultra DMA data out burst 102Sustained Ultra DMA data out burst 10Sustained Ultra DMA data out burstDevice pausing an Ultra DMA data out burst 11Device pausing an Ultra DMA data out burst 104Host terminating an Ultra DMA data out burst 12Host terminating an Ultra DMA data out burstDevice terminating an Ultra DMA data out burst 13Device terminating an Ultra DMA data out burst 106Maintenance Precautions Service And RepairGeneral Information
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