Transcend Information TS16GCF600, TS8GCF600 dimensions Hdmardy, Hstrobe

Page 11

TS8G~16GCF600

 

600X CompactFlash Card

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

Dir.

Pin

Description

-INPACK

O

43

This signal is not used in this mode.

(PC Card Memory Mode except

 

 

 

 

Ultra DMA Protocol Active)

 

 

 

 

 

 

 

 

The Input Acknowledge signal is asserted by the CompactFlash Storage Card

-INPACK

 

 

when the card is selected and responding to an I/O read cycle at the address

(PC Card I/O Mode except Ultra

 

 

that is on the address bus. This signal is used by the host to control the enable of

DMA Protocol Active)

 

 

any input data buffers between the CompactFlash Storage Card and the CPU.

Input Acknowledge

 

 

 

 

 

 

 

 

 

 

Hosts that support a single socket per interface logic, such as for Advanced

 

 

 

 

Timing Modes and Ultra DMA operation may ignore the –INPACK signal from

 

 

 

 

the device and manage their input buffers based solely on Card Enable signals.

-DMARQ

 

 

This signal is a DMA Request that is used for DMA data transfers between host

(PC Card Memory Mode -Ultra

 

 

and device. It shall be asserted by the device when it is ready to transfer data to

DMA Protocol Active)

 

 

or from the host. For Multiword DMA transfers, the direction of data transfer is

-DMARQ

 

 

controlled by -HIOE and -IOWR. This signal is used in a handshake manner with

 

 

(-)DMACK, i.e., the device shall wait until the host asserts (-)DMACK before

(PC Card I/O Mode -Ultra DMA

 

 

 

 

negating (-)DMARQ, and re-asserting (-)DMARQ if there is more data to

Protocol Active)

 

 

 

 

transfer.

 

 

 

 

DMARQ

 

 

In PCMCIA I/O Mode, the -DMARQ shall be ignored by the host while the host is

(True IDE Mode)

 

 

 

 

 

 

performing an I/O Read cycle to the device. The host shall not initiate an I/O

 

 

 

 

Read cycle while -DMARQ is asserted by the device.

 

 

 

 

In True IDE Mode, DMARQ shall not be driven when the device is not selected in

 

 

 

 

the Drive-Head register.

 

 

 

 

While a DMA operation is in progress, -CS0 (-CE1)and -CS1 (-CE2) shall be

 

 

 

 

held negated and the width of the transfers shall be 16 bits.

 

 

 

 

If there is no hardware support for True IDE DMA mode in the host, this output

 

 

 

 

signal is not used and should not be connected at the host. In this case, the

 

 

 

 

BIOS must report that DMA mode is not supported by the host so that device

 

 

 

 

drivers will not attempt DMA mode operation.

 

 

 

 

A host that does not support DMA mode and implements both PC Card and True

 

 

 

 

IDE modes of operation need not alter the PC Card mode connections while in

 

 

 

 

True IDE mode as long as this does not prevent proper operation in any mode.

-HIOE

I

34

This signal is not used in this mode.

(PC Card Memory Mode except

 

 

 

 

Ultra DMA Protocol Active)

 

 

This is an I/O Read strobe generated by the host. This signal gates I/O data onto

 

 

 

 

-HIOE

 

 

the bus from the CompactFlash Storage Card when the card is configured to use

(PC Card I/O Mode except Ultra

 

 

the I/O interface.

DMA Protocol Active)

 

 

 

 

-HIOE

 

 

In True IDE Mode, while Ultra DMA mode is not active, this signal has the same

 

 

function as in PC Card I/O Mode.

(True IDE Mode – Except Ultra

 

 

DMA Protocol Active)

 

 

 

 

-HDMARDY

 

 

In all modes when Ultra DMA mode DMA Read is active, this signal is asserted

 

 

by the host to indicate that the host is ready to receive Ultra DMA data-in bursts.

(All Modes - Ultra DMA Protocol

 

 

The host may negate – HDMARDY to pause an Ultra DMA transfer.

DMA Read)

 

 

 

 

 

 

HSTROBE

 

 

In all modes when Ultra DMA mode DMA Write is active, this signal is the data

 

 

 

 

(All Modes - Ultra DMA Protocol

 

 

out strobe generated by the host. Both the rising and falling edge of HSTROBE

DMA Write)

 

 

cause data to be latched by the device. The host may stop generating

 

 

 

 

HSTROBE edges to pause an Ultra DMA data-out burst.

 

 

 

 

 

 

 

 

 

 

 

Transcend Information Inc.

 

11

 

 

 

 

 

V1.0

Page 10 Page 12
Image 11
Page 10 Page 12
Contents Description Placement FeaturesPower Consumption Dimensions Transcend Block Diagram TS8G~16GCF600 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4PC Card Memory Mode PC Card I/O Mode Output Drive Type Input CharacteristicsInput Leakage Current Symbol Conditions Output Drive Characteristics Output Drive Characteristics 600X CompactFlash Card Signal DescriptionSignal Name Dir Pin Description GND CselHstrobe HdmardyPin Description Signal NameDir Dmack ResetREG Dstrobe IordyDdmardy Electrical Specification Parameter Symbol Input Power Input Characteristics for Udma modeSymbol Output Drive Characteristics for Udma modeSignal Card Host Signal Interface150 a high state per socket Pull-up pin 45 BVD2 to avoid sensing their batteries as LowTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Speed Version 300 ns Symbol Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write TimingIeee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol Min Max SymbolCycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing SpecificationWait Width Time2 TwIORDY TWTLWTH Input Read Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Data Delay from Wait Rising2 TdIORDY TWTHQVCycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationT6Z True IDE PIO Mode Read/Write Timing SpecificationMode TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Mode Udma True IDE Ultra DMA Mode Read/Write Timing SpecificationPC Card MEM PC Card IO Mode Mode UdmaTS8G~16GCF600 Name Name Comment 72.9 50.9 Name Mode Mode4Min Max 14.7Min Max NameSelected Space Card ConfigurationMultiple Function CompactFlash Storage Cards REGInpack REG Hiow Wait Hioe CMD Dmardy StrobeDmarq Dmack Stop Hioe DMADMA CMD REG Attribute Memory FunctionTable Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory REG -CE2 Table Pcmcia Mode I/O FunctionTransfer Function DMA CMDInpack REG Hiow Wait Hioe CMD A00 Table PC Card I/O Mode Udma FunctionDmarq Dmack Stop Hioe Wait DMA A10 CE2 CE1 D15-D8 Common Memory Transfer FunctionTable Common Memory Function DMA REGTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit CommandFormat Track 50h Transcend Information IncErase Sectors C0h Flush Cache E7hBytes Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information Identify Device EchUltra DMA Mode Supported and Selected PIO data transfer cycle timing modeCommand sets supported XXXXh Command sets enabledKey management schemes supported Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode CapabilityWord 49 Capabilities Bit 13 Standby Timer Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackCurrent Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedRecommended Multiword DMA transfer cycle time Word 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Additional Requirements for CF Advanced Timing Modes Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supportedCurrent Multiword DMA timing mode selected Value Current PIO timing mode selectedValue Maximum Pcmcia IO timing mode Supported Value Maximum Memory timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Value Maximum PC Card I/O Udma timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Drive Cyl High Cyl Low Sec Num Sec Cnt Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead DMA C8h Read Long Sector 22h or 23h NOP 00hRead Buffer E4h TS8G~16GCF600 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS8G~16GCF600 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 NOP Error PostingBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR S. Table Capacity Transcend Product Capacity CompactFlash Card Ordering Information
Top Page Image Contents