Transcend Information TS8GCF600 Pull-up pin 45 BVD2 to avoid sensing their batteries as Low

Page 18
￿ Additional Requirements for CF Advanced Timing Modes
state and 100
600X CompactFlash Card
A high state, including pull-up resistor. The card shall be able to drive at least the following load

TS8G~16GCF600

10 while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state. 4) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

10 while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state. 5) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

8) Data Signals: theμ host and each card shall present a load no larger than 50pF 10 at a DC current of 450 A and

10 while meeting all AC timing requirements: 50 pF at a DC current of 400

 

A low state and 1100

 

A high state.

6) BVD2 was not μdefined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall

pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”

μ

 

μ

 

7) Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450

A low state and

 

 

 

 

μ

150 A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing

μ

 

 

 

 

9) Resetμ Signal:μ This signal is pulled up to prevent the input from floating when a CFA to PCMCIAμ adapterμ is used in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test.

requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450 A low state

μ

μ

μ

and 150 A high state per socket).

 

 

 

CF Advancedμ Timing Modes and Ultra DMA Electrical Requirements forμadditional required limitationsμon the implementation of CF Advanced Timing modes and Ultra DMA modes respectively.

150 A high state. The host and each card shall be able to drive at least the following load 10 while meeting all

μ

μ

AC timing requirements: 100pF with DC current 1.6mA low state and 300

A high state. This permits the host to

wire two sockets in parallel without derating the card access speeds.

10) Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for

The CF Advanced Timing modes include PC Card I/O and Memory modes that are 100ns or faster, PC Card Ultra DMA modes 3 or above and True IDE PIO Modes 5,6, Multiword DMA Modes 3,4 and True IDE Ultra DMA modes 3 or above.

When operating in CF Advanced timing modes, the host shall conform to the following requirements:

1)Only one CF device shall be attached to the CF Bus.

2)The host shall not present a load of more than 40pF to the device for all signals, including any cabling.

3)The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported.

4)The -WAIT and IORDY signals shall be ignored by the host.

Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes

Transcend Information Inc.

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V1.0

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Contents Placement Features Power Consumption DimensionsDescription Transcend Block Diagram TS8G~16GCF600 PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Pin Assignments and Pin TypePC Card Memory Mode PC Card I/O Mode Input Characteristics Input Leakage CurrentOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsSymbol Conditions Signal Description Signal Name Dir Pin Description600X CompactFlash Card Csel GNDHdmardy HstrobeSignal Name DirPin Description Reset REGDmack Iordy DdmardyDstrobe Electrical Specification Output Drive Characteristics for Udma mode Input Power Input Characteristics for Udma modeSymbol Parameter SymbolSignal Interface Signal Card HostPull-up pin 45 BVD2 to avoid sensing their batteries as Low 150 a high state per socketUltra DMA Electrical Requirements Series termination required for Ultra DMA operationTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification Speed Version 300 ns Symbol Ieee Symbol Min ns Max nsTable Configuration Register Attribute Memory Write Timing Speed Version 250 ns Symbol Min ns Max nsMin Max Symbol Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol IeeeCommon Memory Write Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsData Delay from Wait Rising2 TdIORDY TWTHQV Input Read Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Wait Width Time2 TwIORDY TWTLWTHOutput Write Timing Specification Cycle Time Mode 255 ns 120 ns 100 ns 80 nsTrue IDE PIO Mode Read/Write Timing Specification ModeT6Z TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 Mode Udma True IDE Ultra DMA Mode Read/Write Timing SpecificationPC Card MEM PC Card IO Mode True IDE Mode UdmaTS8G~16GCF600 Name Name Comment 14.7 Name Mode Mode4Min Max 72.9 50.9Name Min MaxREG Card ConfigurationMultiple Function CompactFlash Storage Cards Selected SpaceDMA Dmardy StrobeDmarq Dmack Stop Hioe Inpack REG Hiow Wait Hioe CMDAttribute Memory Function Table Attribute Memory FunctionDMA CMD REG Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory DMA CMD Table Pcmcia Mode I/O FunctionTransfer Function REG -CE2Table PC Card I/O Mode Udma Function Dmarq Dmack Stop Hioe Wait DMA A10Inpack REG Hiow Wait Hioe CMD A00 DMA REG Common Memory Transfer FunctionTable Common Memory Function CE2 CE1 D15-D8True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Command CodeDefinitions Bit Command Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Cyl High Cyl Low Sec Num Sec Cnt FeatureFlush Cache E7h Transcend Information IncErase Sectors C0h Format Track 50hIdentify Device Ech Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information BytesXXXXh Command sets enabled PIO data transfer cycle timing modeCommand sets supported Ultra DMA Mode Supported and SelectedCF Advanced PC Card I/O and Memory Timing Mode Capability Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting Key management schemes supportedWord 6 Default Number of Sectors per Track Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 49 Capabilities Bit 13 Standby TimerCurrent Number of Cylinders, Heads, Sectors/Track Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current CapacityWords 82-84 Features/command sets supported Recommended Multiword DMA transfer cycle timeWord 68 Minimum PIO transfer cycle time with Iordy Words 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 91 Advanced power management level value Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Value Maximum Multiword DMA timing mode supported Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Additional Requirements for CF Advanced Timing ModesValue Maximum Memory timing mode Supported Value Current PIO timing mode selectedValue Maximum Pcmcia IO timing mode Supported Current Multiword DMA timing mode selectedValue Maximum PC Card I/O Udma timing mode Supported Value Maximum PC Card Memory Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Initialize Drive Parameters 91h Idle 97h or E3hIdle Immediate 95h or E1h Drive Cyl High Cyl Low Sec Num Sec CntNOP 00h Read Buffer E4hRead DMA C8h Read Long Sector 22h or 23h TS8G~16GCF600 Seek 7Xh Set Features EFh Request Sense 03hFeature Supported TS8G~16GCF600 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 Error Posting BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERRNOP S. Table Capacity Ordering Information Transcend Product Capacity CompactFlash Card
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