Transcend Information TS8GCF600, TS16GCF600 Device Control Register Address 3F6h376h Offset Eh

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TS8G~16GCF600		600X CompactFlash Card

Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset.

Bit 0: this bit is ignored by the CompactFlash Storage Card.

Transcend Information Inc.

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Contents Description Placement FeaturesPower Consumption Dimensions Transcend Block Diagram TS8G~16GCF600 PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Pin Assignments and Pin TypePC Card Memory Mode PC Card I/O Mode Output Drive Type Input CharacteristicsInput Leakage Current Symbol Conditions Output Drive CharacteristicsOutput Drive Characteristics 600X CompactFlash Card Signal DescriptionSignal Name Dir Pin Description Csel GNDHdmardy HstrobePin Description Signal NameDir Dmack ResetREG Dstrobe IordyDdmardy Electrical Specification Input Power Input Characteristics for Udma mode SymbolOutput Drive Characteristics for Udma mode Parameter SymbolSignal Interface Signal Card HostPull-up pin 45 BVD2 to avoid sensing their batteries as Low 150 a high state per socketTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification Speed Version 300 ns Symbol Ieee Symbol Min ns Max nsTable Configuration Register Attribute Memory Write Timing Speed Version 250 ns Symbol Min ns Max nsCommon Memory Read Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 ns SymbolMin Max Symbol IeeeCommon Memory Write Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsInput Read Timing Specification Data Delay after Hioe TdHIOE TlGLQVData Delay from Wait Rising2 TdIORDY TWTHQV Wait Width Time2 TwIORDY TWTLWTHOutput Write Timing Specification Cycle Time Mode 255 ns 120 ns 100 ns 80 nsT6Z True IDE PIO Mode Read/Write Timing SpecificationMode TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Ultra DMA Mode Read/Write Timing Specification PC Card MEM PC Card IO ModeMode Udma True IDE Mode UdmaTS8G~16GCF600 Name Name Comment Name Mode Mode4 Min Max14.7 72.9 50.9Name Min MaxCard Configuration Multiple Function CompactFlash Storage CardsREG Selected SpaceDmardy Strobe Dmarq Dmack Stop HioeDMA Inpack REG Hiow Wait Hioe CMDDMA CMD REG Attribute Memory FunctionTable Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionDMA CMD REG -CE2Inpack REG Hiow Wait Hioe CMD A00 Table PC Card I/O Mode Udma FunctionDmarq Dmack Stop Hioe Wait DMA A10 Common Memory Transfer Function Table Common Memory FunctionDMA REG CE2 CE1 D15-D8True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Feature Register Address 1F1h171h Offset 1, 0Dh Write Only Sector Count Register Address 1F2h172h OffsetSector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Command CodeDefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureTranscend Information Inc Erase Sectors C0hFlush Cache E7h Format Track 50hDrive Cyl High Cyl Low Sec Num Sec Cnt Feature Word Default Total Data Field Type InformationIdentify Device Ech BytesPIO data transfer cycle timing mode Command sets supportedXXXXh Command sets enabled Ultra DMA Mode Supported and SelectedWord 0 General Configuration CF Advanced True IDE Timing Mode Capability and SettingCF Advanced PC Card I/O and Memory Timing Mode Capability Key management schemes supportedWord 1 Default Number of Cylinders Word 3 Default Number of HeadsWord 6 Default Number of Sectors per Track Word 49 Capabilities Bit 13 Standby TimerMultiple Sector Setting Total Sectors Addressable in LBA ModeCurrent Number of Cylinders, Heads, Sectors/Track Current CapacityWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedRecommended Multiword DMA transfer cycle time Words 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Word 160 Power Requirement Description Value Maximum PIO mode timing selectedValue Maximum Multiword DMA timing mode supported Additional Requirements for CF Advanced Timing ModesValue Current PIO timing mode selected Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported Current Multiword DMA timing mode selectedValue PC Card Memory or I/O Udma timing mode Selected Value Maximum PC Card I/O Udma timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Idle 97h or E3h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Drive Cyl High Cyl Low Sec Num Sec CntRead DMA C8h Read Long Sector 22h or 23h NOP 00hRead Buffer E4h TS8G~16GCF600 Seek 7Xh Set Features EFh Request Sense 03hFeature Supported TS8G~16GCF600 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 NOP Error PostingBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR S. Table Capacity Ordering Information Transcend Product Capacity CompactFlash Card