Transcend Information TS16GCF600, TS8GCF600 dimensions TS8G~16GCF600

Page 55

TS8G~16GCF600

600X CompactFlash Card

 

 

 

Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode.

Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode.

Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode.

Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.

￿Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh) These registers return the CompactFlash Storage Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows:

Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command.

Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.

Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation.

Bit 1 (IDX): This bit is always set to 0.

Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers.

Transcend Information Inc.

55

V1.0

Page 54 Page 56
Image 55
Page 54 Page 56
Contents Power Consumption Dimensions Placement FeaturesDescription Transcend Block Diagram TS8G~16GCF600 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4PC Card Memory Mode PC Card I/O Mode Input Leakage Current Input CharacteristicsOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsSymbol Conditions Signal Name Dir Pin Description Signal Description600X CompactFlash Card GND CselHstrobe HdmardyDir Signal NamePin Description REG ResetDmack Ddmardy IordyDstrobe Electrical Specification Parameter Symbol Input Power Input Characteristics for Udma modeSymbol Output Drive Characteristics for Udma modeSignal Card Host Signal Interface150 a high state per socket Pull-up pin 45 BVD2 to avoid sensing their batteries as LowSeries termination required for Ultra DMA operation Ultra DMA Electrical RequirementsTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Speed Version 300 ns Symbol Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write TimingIeee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol Min Max SymbolCycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing SpecificationWait Width Time2 TwIORDY TWTLWTH Input Read Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Data Delay from Wait Rising2 TdIORDY TWTHQVCycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationMode True IDE PIO Mode Read/Write Timing SpecificationT6Z TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Mode Udma True IDE Ultra DMA Mode Read/Write Timing SpecificationPC Card MEM PC Card IO Mode Mode UdmaTS8G~16GCF600 Name Name Comment 72.9 50.9 Name Mode Mode4Min Max 14.7Min Max NameSelected Space Card ConfigurationMultiple Function CompactFlash Storage Cards REGInpack REG Hiow Wait Hioe CMD Dmardy StrobeDmarq Dmack Stop Hioe DMATable Attribute Memory Function Attribute Memory FunctionDMA CMD REG Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory REG -CE2 Table Pcmcia Mode I/O FunctionTransfer Function DMA CMDDmarq Dmack Stop Hioe Wait DMA A10 Table PC Card I/O Mode Udma FunctionInpack REG Hiow Wait Hioe CMD A00 CE2 CE1 D15-D8 Common Memory Transfer FunctionTable Common Memory Function DMA REGTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit CommandFormat Track 50h Transcend Information IncErase Sectors C0h Flush Cache E7hBytes Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information Identify Device EchUltra DMA Mode Supported and Selected PIO data transfer cycle timing modeCommand sets supported XXXXh Command sets enabledKey management schemes supported Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode CapabilityWord 49 Capabilities Bit 13 Standby Timer Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackCurrent Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackRecommended Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedWord 68 Minimum PIO transfer cycle time with Iordy Word 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 128 Security Status Bit 8 Security Level Additional Requirements for CF Advanced Timing Modes Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supportedCurrent Multiword DMA timing mode selected Value Current PIO timing mode selectedValue Maximum Pcmcia IO timing mode Supported Value Maximum Memory timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Value Maximum PC Card I/O Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Drive Cyl High Cyl Low Sec Num Sec Cnt Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead Buffer E4h NOP 00hRead DMA C8h Read Long Sector 22h or 23h TS8G~16GCF600 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS8G~16GCF600 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Error PostingNOP S. Table Capacity Transcend Product Capacity CompactFlash Card Ordering Information
Top Page Image Contents