Transcend Information TS8GCF600, TS16GCF600 dimensions Name, Min Max

Page 36

TS8G~16GCF600

600X CompactFlash Card

 

 

 

Name

SRISE

SFALL

Comment

Rising Edge Slew Rate for any signal

Falling Edge Slew Rate for any signal

Min

Max

Notes

[V/ns]

[V/ns]

 

 

 

 

1.251

1.251

Note: 1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender’s series termination resistor and one half inch or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within one half inch of the connector.

The test load and test points should then be soldered directly to the exposed source side connectors. The test loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the test point to ground. Slew rates shall be met for both capacitor values.

Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500 MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge.

Transcend Information Inc.

36

V1.0

Image 36
Contents Placement Features Power Consumption DimensionsDescription Transcend Block Diagram TS8G~16GCF600 PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Pin Assignments and Pin TypePC Card Memory Mode PC Card I/O Mode Input Characteristics Input Leakage CurrentOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsSymbol Conditions Signal Description Signal Name Dir Pin Description600X CompactFlash Card Csel GNDHdmardy HstrobeSignal Name DirPin Description Reset REGDmack Iordy DdmardyDstrobe Electrical Specification Input Power Input Characteristics for Udma mode SymbolOutput Drive Characteristics for Udma mode Parameter SymbolSignal Interface Signal Card HostPull-up pin 45 BVD2 to avoid sensing their batteries as Low 150 a high state per socketUltra DMA Electrical Requirements Series termination required for Ultra DMA operationTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification Speed Version 300 ns Symbol Ieee Symbol Min ns Max nsTable Configuration Register Attribute Memory Write Timing Speed Version 250 ns Symbol Min ns Max nsCommon Memory Read Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 ns SymbolMin Max Symbol IeeeCommon Memory Write Timing Specification Cycle Time Mode 250 ns 120 ns 100 ns 80 nsInput Read Timing Specification Data Delay after Hioe TdHIOE TlGLQVData Delay from Wait Rising2 TdIORDY TWTHQV Wait Width Time2 TwIORDY TWTLWTHOutput Write Timing Specification Cycle Time Mode 255 ns 120 ns 100 ns 80 nsTrue IDE PIO Mode Read/Write Timing Specification ModeT6Z TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Ultra DMA Mode Read/Write Timing Specification PC Card MEM PC Card IO ModeMode Udma True IDE Mode UdmaTS8G~16GCF600 Name Name Comment Name Mode Mode4 Min Max14.7 72.9 50.9Name Min MaxCard Configuration Multiple Function CompactFlash Storage CardsREG Selected SpaceDmardy Strobe Dmarq Dmack Stop HioeDMA Inpack REG Hiow Wait Hioe CMDAttribute Memory Function Table Attribute Memory FunctionDMA CMD REG Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionDMA CMD REG -CE2Table PC Card I/O Mode Udma Function Dmarq Dmack Stop Hioe Wait DMA A10Inpack REG Hiow Wait Hioe CMD A00 Common Memory Transfer Function Table Common Memory FunctionDMA REG CE2 CE1 D15-D8True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Feature Register Address 1F1h171h Offset 1, 0Dh Write Only Sector Count Register Address 1F2h172h OffsetSector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Command CodeDefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureTranscend Information Inc Erase Sectors C0hFlush Cache E7h Format Track 50hDrive Cyl High Cyl Low Sec Num Sec Cnt Feature Word Default Total Data Field Type InformationIdentify Device Ech BytesPIO data transfer cycle timing mode Command sets supportedXXXXh Command sets enabled Ultra DMA Mode Supported and SelectedWord 0 General Configuration CF Advanced True IDE Timing Mode Capability and SettingCF Advanced PC Card I/O and Memory Timing Mode Capability Key management schemes supportedWord 1 Default Number of Cylinders Word 3 Default Number of HeadsWord 6 Default Number of Sectors per Track Word 49 Capabilities Bit 13 Standby TimerMultiple Sector Setting Total Sectors Addressable in LBA ModeCurrent Number of Cylinders, Heads, Sectors/Track Current CapacityWords 82-84 Features/command sets supported Recommended Multiword DMA transfer cycle timeWord 68 Minimum PIO transfer cycle time with Iordy Words 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 91 Advanced power management level value Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 160 Power Requirement Description Value Maximum PIO mode timing selectedValue Maximum Multiword DMA timing mode supported Additional Requirements for CF Advanced Timing ModesValue Current PIO timing mode selected Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported Current Multiword DMA timing mode selectedValue Maximum PC Card I/O Udma timing mode Supported Value Maximum PC Card Memory Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Idle 97h or E3h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Drive Cyl High Cyl Low Sec Num Sec CntNOP 00h Read Buffer E4hRead DMA C8h Read Long Sector 22h or 23h TS8G~16GCF600 Seek 7Xh Set Features EFh Request Sense 03hFeature Supported TS8G~16GCF600 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 Error Posting BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERRNOP S. Table Capacity Ordering Information Transcend Product Capacity CompactFlash Card