Transcend Information TS16GCF600, TS8GCF600 dimensions Name Mode Mode4, Min Max, 14.7, 72.9 50.9

Page 35

TS8G~16GCF600

600X CompactFlash Card

 

 

 

Notes: 1) The parameters tUI, tMLI : (Ultra DMA Data-In Burst Device Termination Timing and Ultra DMA Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.

2)80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes greater than 2.

3)Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 4)For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDY- giving it a known state when released.

5)The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable. This could result in the minimum values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.

 

UDMA

 

UDMA

 

UDMA

 

UDMA

 

UDMA

UDMA

UDMA

Name

Mode 0

 

Mode 1

 

Mode 2

 

Mode 3

 

Mode4

Mode 5

Mode 6

 

(ns)

 

(ns)

 

(ns)

 

(ns)

 

(ns)

(ns)

(ns)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

 

Max

Min

 

Max

Min

 

Max

Min

 

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDSIC

14.7

 

 

9.7

 

 

6.8

 

 

6.8

 

 

4.8

 

2.3

 

2.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDHIC

4.8

 

 

4.8

 

 

4.8

 

 

4.8

 

 

4.8

 

2.8

 

2.8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDVSIC

72.9

 

 

50.9

 

 

33.9

 

 

22.6

 

 

9.5

 

6.0

 

5.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDVHIC

9.0

 

 

9.0

 

 

9.0

 

 

9.0

 

 

9.0

 

6.0

 

5.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDSIC

Recipient IC data setup time (from data valid until STROBE edge) (see note 2)

 

 

 

 

 

 

 

 

tDHIC

Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2)

 

 

tDVSIC

Sender IC data valid setup time (from data valid until STROBE edge) (see note 3)

tDVHIC

Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)

Notes: 1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.

2)The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured through 1.5 V).

3)The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values.

Transcend Information Inc.

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V1.0

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Contents Description Placement FeaturesPower Consumption Dimensions Transcend Block Diagram TS8G~16GCF600 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4PC Card Memory Mode PC Card I/O Mode Output Drive Type Input CharacteristicsInput Leakage Current Symbol Conditions Output Drive CharacteristicsOutput Drive Characteristics 600X CompactFlash Card Signal DescriptionSignal Name Dir Pin Description GND CselHstrobe HdmardyPin Description Signal NameDir Dmack ResetREG Dstrobe IordyDdmardy Electrical Specification Parameter Symbol Input Power Input Characteristics for Udma modeSymbol Output Drive Characteristics for Udma modeSignal Card Host Signal Interface150 a high state per socket Pull-up pin 45 BVD2 to avoid sensing their batteries as LowTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Speed Version 300 ns Symbol Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write TimingIeee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol Min Max SymbolCycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing SpecificationWait Width Time2 TwIORDY TWTLWTH Input Read Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Data Delay from Wait Rising2 TdIORDY TWTHQVCycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationT6Z True IDE PIO Mode Read/Write Timing SpecificationMode TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Mode Udma True IDE Ultra DMA Mode Read/Write Timing SpecificationPC Card MEM PC Card IO Mode Mode UdmaTS8G~16GCF600 Name Name Comment 72.9 50.9 Name Mode Mode4Min Max 14.7Min Max NameSelected Space Card ConfigurationMultiple Function CompactFlash Storage Cards REGInpack REG Hiow Wait Hioe CMD Dmardy StrobeDmarq Dmack Stop Hioe DMADMA CMD REG Attribute Memory FunctionTable Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory REG -CE2 Table Pcmcia Mode I/O FunctionTransfer Function DMA CMDInpack REG Hiow Wait Hioe CMD A00 Table PC Card I/O Mode Udma FunctionDmarq Dmack Stop Hioe Wait DMA A10 CE2 CE1 D15-D8 Common Memory Transfer FunctionTable Common Memory Function DMA REGTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit CommandFormat Track 50h Transcend Information IncErase Sectors C0h Flush Cache E7hBytes Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information Identify Device EchUltra DMA Mode Supported and Selected PIO data transfer cycle timing modeCommand sets supported XXXXh Command sets enabledKey management schemes supported Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode CapabilityWord 49 Capabilities Bit 13 Standby Timer Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackCurrent Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedRecommended Multiword DMA transfer cycle time Word 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Additional Requirements for CF Advanced Timing Modes Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supportedCurrent Multiword DMA timing mode selected Value Current PIO timing mode selectedValue Maximum Pcmcia IO timing mode Supported Value Maximum Memory timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Value Maximum PC Card I/O Udma timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Drive Cyl High Cyl Low Sec Num Sec Cnt Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead DMA C8h Read Long Sector 22h or 23h NOP 00hRead Buffer E4h TS8G~16GCF600 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS8G~16GCF600 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 NOP Error PostingBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR S. Table Capacity Transcend Product Capacity CompactFlash Card Ordering Information
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