Transcend Information TS16GCF600 CF-ATA Registers, Data Register Address 1F0h170hOffset 0,8,9

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TS8G~16GCF600		600X CompactFlash Card

CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the “task file.”

Data Register (Address - 1F0h[170h];Offset 0,8,9)

The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register.

Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)

This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register.

This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low and -CE1 high.

Bit 7 (BBK/ICRC): this bit is set when a Bad Block is detected. This bit is also set when an interface CRC error is detected in True IDE Ultra DMA modes of operation.

Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.

Bit 5: this bit is 0.

Bit 4 (IDNF): the requested sector ID is in error or cannot be found.

Bit 3: this bit is 0.

Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued.

Bit 1 This bit is 0.

Bit 0 (AMNF) This bit is set in case of a general error.

Transcend Information Inc.

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Contents Description Placement FeaturesPower Consumption Dimensions Transcend Block Diagram TS8G~16GCF600 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4PC Card Memory Mode PC Card I/O Mode Output Drive Type Input CharacteristicsInput Leakage Current Symbol Conditions Output Drive CharacteristicsOutput Drive Characteristics 600X CompactFlash Card Signal DescriptionSignal Name Dir Pin Description GND CselHstrobe HdmardyPin Description Signal NameDir Dmack ResetREG Dstrobe IordyDdmardy Electrical Specification Symbol Input Power Input Characteristics for Udma modeOutput Drive Characteristics for Udma mode Parameter SymbolSignal Card Host Signal Interface150 a high state per socket Pull-up pin 45 BVD2 to avoid sensing their batteries as LowTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Speed Version 300 ns Symbol Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write TimingCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol Common Memory Read Timing SpecificationMin Max Symbol IeeeCycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Input Read Timing SpecificationData Delay from Wait Rising2 TdIORDY TWTHQV Wait Width Time2 TwIORDY TWTLWTHCycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationT6Z True IDE PIO Mode Read/Write Timing SpecificationMode TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 PC Card MEM PC Card IO Mode True IDE Ultra DMA Mode Read/Write Timing SpecificationMode Udma True IDE Mode UdmaTS8G~16GCF600 Name Name Comment Min Max Name Mode Mode414.7 72.9 50.9Min Max NameMultiple Function CompactFlash Storage Cards Card ConfigurationREG Selected SpaceDmarq Dmack Stop Hioe Dmardy StrobeDMA Inpack REG Hiow Wait Hioe CMDDMA CMD REG Attribute Memory FunctionTable Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionDMA CMD REG -CE2Inpack REG Hiow Wait Hioe CMD A00 Table PC Card I/O Mode Udma FunctionDmarq Dmack Stop Hioe Wait DMA A10 Table Common Memory Function Common Memory Transfer FunctionDMA REG CE2 CE1 D15-D8True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersSector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Execute Drive Diagnostic 90h Check Power Mode 98h or E5hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureErase Sectors C0h Transcend Information IncFlush Cache E7h Format Track 50hWord Default Total Data Field Type Information Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdentify Device Ech BytesCommand sets supported PIO data transfer cycle timing modeXXXXh Command sets enabled Ultra DMA Mode Supported and SelectedCF Advanced True IDE Timing Mode Capability and Setting Word 0 General ConfigurationCF Advanced PC Card I/O and Memory Timing Mode Capability Key management schemes supportedWord 3 Default Number of Heads Word 1 Default Number of CylindersWord 6 Default Number of Sectors per Track Word 49 Capabilities Bit 13 Standby TimerTotal Sectors Addressable in LBA Mode Multiple Sector SettingCurrent Number of Cylinders, Heads, Sectors/Track Current CapacityWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedRecommended Multiword DMA transfer cycle time Word 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Value Maximum PIO mode timing selected Word 160 Power Requirement DescriptionValue Maximum Multiword DMA timing mode supported Additional Requirements for CF Advanced Timing ModesValue Maximum Pcmcia IO timing mode Supported Value Current PIO timing mode selectedValue Maximum Memory timing mode Supported Current Multiword DMA timing mode selectedValue PC Card Memory or I/O Udma timing mode Selected Value Maximum PC Card I/O Udma timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Idle Immediate 95h or E1h Idle 97h or E3hInitialize Drive Parameters 91h Drive Cyl High Cyl Low Sec Num Sec CntRead DMA C8h Read Long Sector 22h or 23h NOP 00hRead Buffer E4h TS8G~16GCF600 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS8G~16GCF600 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 NOP Error PostingBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR S. Table Capacity Transcend Product Capacity CompactFlash Card Ordering Information