Transcend Information TS16GCF600 True IDE Ultra DMA Mode Read/Write Timing Specification

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TS8G~16GCF600

600X CompactFlash Card

 

 

 

￿True IDE Ultra DMA Mode Read/Write Timing Specification

Ultra DMA operations can take place in any of the three basic interface modes: PC Card Memory mode, PC Card I/O mode, and True IDE (the original mode to support UDMA). The usage of signals in each of the modes is shown in Table 24:Ultra DMA Signal Usage In Each Interface Mode

 

 

Pin # (Non

PC CARD MEM

PC CARD IO MODE

UDMA Signal

Type

UDMA MEM

MODE UDMA

UDMA

 

 

MODE)

 

 

 

 

DMARQ

Output

43 (-INPACK)

-DMARQ

-DMARQ

 

 

 

 

 

HREG

Input

44 (-REG)

-DMACK

DMACK

 

 

 

 

 

HIOW

Input

35 (-HIOW)

STOP 1

STOP 1

HIOE

Input

34 (-HIOE)

-HDMARDY(R) 1,

-HDMARDY(R) 1, 2

2HSTROBE(W) 1, 3, 4

HSTROBE(W) 1, 3, 4

 

 

 

 

 

IORDY

Output

42 (-WAIT)

-DDMARDY(W) 1, 3

-DDMARDY(W) 1, 3

DSTROBE(R) 1. 2. 4

DSTROBE(R) 1. 2. 4

 

 

 

 

 

HD [15:0]

Bidir

… (D[15:00])

D[15:00]

D[15:00]

 

 

 

 

 

HA [10:0]

Input

… (A[10:00])

A[10:00]

A[10:00]

 

 

 

 

 

CSEL

Input

39 (-CSEL)

-CSEL

-CSEL

HIRQ

Output

37 (READY)

READY

-INTRQ

CE1

Input

7 (-CE1)

-CE1

-CE1

CE2

31 (-CE2)

-CE2

-CE2

 

 

 

 

 

 

TRUE IDE MODE

UDMA

DMARQ

-DMACK

STOP 1

-HDMARDY(R) 1, 2 HSTROBE(W) 1, 3, 4

-DDMARDY(W) 1, 3 DSTROBE(R) 1. 2. 4

D[15:00]

A[02:00] 5

-CSEL

INTRQ

-CS0 -CS1

Notes:1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.

2)The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.

3)The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.

4)The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.

5)Address lines 03 through 10 are not used in True IDE mode.

Several signal lines are redefined to provide different functions during an Ultra DMA data burst. These lines assume their UDMA definitions when:

1an Ultra DMA mode is selected, and

2a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and

3 the device asserts (-)DMARQ, and

4 the host asserts (-)DMACK.

These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of -DMACK by the host at the termination of an Ultra DMA data burst.

With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst.

During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data.

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less than or

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Contents Power Consumption Dimensions Placement FeaturesDescription Transcend Block Diagram TS8G~16GCF600 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4PC Card Memory Mode PC Card I/O Mode Input Leakage Current Input CharacteristicsOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsSymbol Conditions Signal Name Dir Pin Description Signal Description600X CompactFlash Card GND CselHstrobe HdmardyDir Signal NamePin Description REG ResetDmack Ddmardy IordyDstrobe Electrical Specification Parameter Symbol Input Power Input Characteristics for Udma modeSymbol Output Drive Characteristics for Udma modeSignal Card Host Signal Interface150 a high state per socket Pull-up pin 45 BVD2 to avoid sensing their batteries as LowSeries termination required for Ultra DMA operation Ultra DMA Electrical RequirementsTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Speed Version 300 ns Symbol Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write TimingIeee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol Min Max SymbolCycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing SpecificationWait Width Time2 TwIORDY TWTLWTH Input Read Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Data Delay from Wait Rising2 TdIORDY TWTHQVCycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationMode True IDE PIO Mode Read/Write Timing SpecificationT6Z TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Mode Udma True IDE Ultra DMA Mode Read/Write Timing SpecificationPC Card MEM PC Card IO Mode Mode UdmaTS8G~16GCF600 Name Name Comment 72.9 50.9 Name Mode Mode4Min Max 14.7Min Max NameSelected Space Card ConfigurationMultiple Function CompactFlash Storage Cards REGInpack REG Hiow Wait Hioe CMD Dmardy StrobeDmarq Dmack Stop Hioe DMATable Attribute Memory Function Attribute Memory FunctionDMA CMD REG Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory REG -CE2 Table Pcmcia Mode I/O FunctionTransfer Function DMA CMDDmarq Dmack Stop Hioe Wait DMA A10 Table PC Card I/O Mode Udma FunctionInpack REG Hiow Wait Hioe CMD A00 CE2 CE1 D15-D8 Common Memory Transfer FunctionTable Common Memory Function DMA REGTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit CommandFormat Track 50h Transcend Information IncErase Sectors C0h Flush Cache E7hBytes Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information Identify Device EchUltra DMA Mode Supported and Selected PIO data transfer cycle timing modeCommand sets supported XXXXh Command sets enabledKey management schemes supported Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode CapabilityWord 49 Capabilities Bit 13 Standby Timer Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackCurrent Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackRecommended Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedWord 68 Minimum PIO transfer cycle time with Iordy Word 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 128 Security Status Bit 8 Security Level Additional Requirements for CF Advanced Timing Modes Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supportedCurrent Multiword DMA timing mode selected Value Current PIO timing mode selectedValue Maximum Pcmcia IO timing mode Supported Value Maximum Memory timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Value Maximum PC Card I/O Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Drive Cyl High Cyl Low Sec Num Sec Cnt Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead Buffer E4h NOP 00hRead DMA C8h Read Long Sector 22h or 23h TS8G~16GCF600 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS8G~16GCF600 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Error PostingNOP S. Table Capacity Transcend Product Capacity CompactFlash Card Ordering Information
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