Xilinx UG154 manual Additional Core Resources, Technical Support, Feedback, Document

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Chapter 1: Introduction

Contact your local Xilinx representative for a closer review and estimate of the effort required to meet your specific design requirements.

Additional Core Resources

For detailed information and updates about the SPI-4.2 core, see the following additional documents located on the SPI-4.2 product page.

•LogiCORE SPI-4.2 Data Sheet

•LogiCORE SPI-4.2 Release Notes

•LogiCORE SPI-4.2 User Guide

For updates to this document, see the LogiCORE SPI-4.2 Getting Started Guide, also located on the Xilinx SPI-4.2 product page.

Technical Support

To obtain technical support specific to the SPI-4.2 core, visit http://support.xilinx.com/. Questions are routed to a team of engineers with expertise using the SPI-4.2 core.

Xilinx will provide technical support for use of this product as described in the SPI-4.2 User Guide and the SPI-4.2 Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs outside the guidelines presented in this document.

Feedback

Xilinx welcomes comments and suggestions about the SPI-4.2 core and the documentation provided with the core.

Core

For comments or suggestions about the SPI-4.2 core, please submit a WebCase from

http://support.xilinx.com/. Be sure to include the following information:

•Product name

•Core version number

•Explanation of your comments

Document

For comments or suggestions about this document, please submit a WebCase from

http://support.xilinx.com/. Be sure to include the following information:

•Document title

•Document number

•Page number(s) to which your comments refer

•Explanation of your comments

14	www.xilinx.com	SPI-4.2 v8.5 Getting Started Guide
		UG154 March 24, 2008

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Contents LogiCORE IP SPI-4.2 Core UG154 March 24SPI-4.2 v8.5 Getting Started Guide Revision History Date Version RevisionSPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details Schedule of Figures 1Core Customization GUI Main WindowSPI-4.2 v8.5 Getting Started Guide Schedule of Tables Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2SPI-4.2 v8.5 Getting Started Guide Conventions Contents About This Guide Preface About This Guide TypographicalOnline Document Convention Meaning or Use ExampleAbout the Core IntroductionSystem Requirements Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support CoreLicense Options Licensing the CoreBefore you Begin Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview Quick Start Example Design 1Core Customization GUI Main WindowRunning the Simulation Setting up for SimulationImplementing the Example Design Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Detailed Example Design Project directoryDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design Component name/implement 5Implement Directory Name DescriptionComponent name/simulation Directory and File ContentsImplement/results 6Results Directory Name DescriptionSimulation/functional 8Functional Directory Name DescriptionImplementation and Simulation Scripts Implementation and Simulation ScriptsSimulation/timing 9Timing Directory Name DescriptionExample Design Configuration Simulation Script DetailsBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Demonstration Test Bench ConnectionsClock Generator Demonstration Test Bench4Startup State Diagram Startup ModuleStimulus Module Calendar LoaderStatus Monitor Procedures ModuleData Monitor Test Case Package Constant Default Value DescriptionCustomizing the Demonstration Test Bench 10Testcase Package User-Defined ConstantsTestdatafile Constant Default Value Description Type Range Testcase Module11Useful Testcase Signals Name Description 12Testcase Module Request Signals Name FunctionCalendar Sequence Files Sink and Source Detailed Example Design Procedures Module Vhdl DetailsTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Appendix B Verilog Details Table B-3sendidles cycles Inputs Name Range DescriptionRandom Testcase Sample Code Table B-7getstatus channel Inputs Range DescriptionAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings Timing Simulation Warning and Error Messages SETUP, HOLD, Recovery violation on /XFFAppendix D Timing Simulation Warning and Error Messages