Xilinx UG154 manual Revision History, Date Version Revision

Page 3

Revision History

The following table shows the revision history for this document.

Date	Version	Revision

09/30/04	1.0	Initial Xilinx release.

11/11/04	1.1	Document updated to support SPI-4.2 core v7.1.

04/28/05	1.2	Document updated to support SPI-4.2 core v7.2 and Xilinx ISE v7.1i.

08/31/05	2.0	Updated ISE service pack information.

1/18/06	3.0	Updated ISE to v8.1i, release date

7/13/06	4.0	Added support for Virtex-5, ISE to v8.2i, advanced version number and release date.

9/21/06	4.1	Updted for IP2i minor release. Removed Simulating the Dynamic Alignment Sink
		core section from the example design chapter.

2/15/07	4.2	Updated system requirements, ISE version, and applied new directory structure
		template to Chapter 4.

8/08/07	4.3	Updated for IP1 Jade Minor release. ISE version to 9.2i.

3/24/08	4.4	Updated core to v8.5, updated supported tool versions, and release date.

www.xilinx.com	SPI-4.2 v8.5 Getting Started Guide
	UG154 March 24, 2008

Image 3

Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Contents About This GuideConventions Convention Meaning or Use Example TypographicalOnline Document Preface About This GuideRecommended Design Experience IntroductionSystem Requirements About the CoreCore Additional Core ResourcesTechnical Support FeedbackSimulation-Only Evaluation Licensing the CoreBefore you Begin License OptionsObtaining Your License FullLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Quick Start Example Design OverviewGenerating the Core 1Core Customization GUI Main Window Quick Start Example DesignFunctional Simulation Setting up for SimulationImplementing the Example Design Running the SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents Directory and File Contents 3Doc Directory Component name/example design4Example Design Directory Name Description 5Implement Directory Name Description Component name/implement6Results Directory Name Description Directory and File ContentsImplement/results Component name/simulation8Functional Directory Name Description Simulation/functional9Timing Directory Name Description Implementation and Simulation ScriptsSimulation/timing Implementation and Simulation ScriptsSimulation Script Details Example Design ConfigurationExample Design Configuration Loopback ModuleBasic Loopback Operation Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleProcedures Module Data MonitorStatus Monitor 10Testcase Package User-Defined Constants Constant Default Value DescriptionCustomizing the Demonstration Test Bench Test Case PackageTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages