Xilinx UG154 Licensing the Core, Before you Begin, License Options, Simulation-Only Evaluation

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Chapter 2

Licensing the Core

This chapter provides instructions for obtaining a license for the core so that you can use the core in a design. The SPI-4.2 core is provided under the terms of the Xilinx LogiCORE Site License Agreement. This license agreement conforms to the terms of the SignOnce IP License standard defined by the Common License Consortium. Purchase of the core entitles you to technical support and access to updates for a period of one year.

Before you Begin

This chapter assumes that you have installed the core using either the CORE GeneratorTM IP Update installer or by performing a manual installation after downloading the core from the web. For information about installing the core, see the SPI-4.2 product page.

Before installing the core, you must have a Xilinx.com account and the ISE 10.1 software installed on your system.

To set up an account and install the ISE software:

1.Click Sign in to Access Account at the top of the Xilinx home page; then follow the instructions to create a support account.

2.Install the ISE 10.1 software with the applicable service pack.

License Options

The SPI-4.2 core provides three licensing options, described below.

Simulation-Only Evaluation

The Simulation-Only Evaluation license is provided with the Xilinx CORE Generator system. This license lets you evaluate core functionality using a provided example design. You can also use your own design and simulate the various interfaces on the core. Functional simulation is supported by a dynamically generated gate-level netlist.

Full System Hardware Evaluation

The Full System Hardware Evaluation license is available at no cost and lets you fully integrate the core into an FPGA design, place and route the design, evaluate timing, and perform back-annotated gate-level simulation using the demonstration test bench provided.

In addition, the license lets you generate a bitstream from the placed and routed design, which can then be downloaded to a supported device and tested in hardware. The core can

SPI-4.2 v8.5 Getting Started Guide

www.xilinx.com

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Contents About This GuideConventions Convention Meaning or Use Example TypographicalOnline Document Preface About This GuideRecommended Design Experience IntroductionSystem Requirements About the CoreCore Additional Core ResourcesTechnical Support FeedbackSimulation-Only Evaluation Licensing the CoreBefore you Begin License OptionsObtaining Your License FullLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Quick Start Example Design OverviewGenerating the Core 1Core Customization GUI Main Window Quick Start Example DesignFunctional Simulation Setting up for SimulationImplementing the Example Design Running the SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents Directory and File Contents 3Doc Directory Component name/example design4Example Design Directory Name Description 5Implement Directory Name Description Component name/implement6Results Directory Name Description Directory and File ContentsImplement/results Component name/simulation8Functional Directory Name Description Simulation/functional9Timing Directory Name Description Implementation and Simulation ScriptsSimulation/timing Implementation and Simulation ScriptsSimulation Script Details Example Design ConfigurationExample Design Configuration Loopback ModuleBasic Loopback Operation Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleProcedures Module Data MonitorStatus Monitor 10Testcase Package User-Defined Constants Constant Default Value DescriptionCustomizing the Demonstration Test Bench Test Case PackageTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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