Xilinx UG154 manual Procedures Module, Data Monitor, Status Monitor

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Chapter 4: Detailed Example Design

Procedures Module

The procedures module is a package of functions instantiated in the testcase module to simplify sending data and status to the stimulus module. Using these functions, you can create any desired sequence of data or status. The method by which functions are called varies among languages, and is described in the appendices.

The following functions are supported in the procedures module:

•send_packet Used to transmit an entire packet of data. This procedure will always send an SOP control word before the burst of data and an EOP control word following the data burst.

•send_user_data Used to transmit a burst of data. The presence of an SOP control word (before the burst of data) and an EOP control word (following the data burst) can be specified. The EOP can optionally specify an abort (ERR).

•send_idles Used to send idle cycles.

•send_training Used to send training patterns.

•sop_spacing Used to send erred data by sending two SOP words in less than eight cycles. This function limits the number of cycles between the two SOPs to less than seven. This ensures that an SOP spacing error occurs.

•reset Used to reset the interface to the stimulus module. Should be called at the beginning of any testcase.

•send_status Used to change the status (on TStat) for a particular channel.

•get_status Used to check the status of a specific channel.

Data Monitor

The data monitor is responsible for verifying that data sent from the demonstration test bench is the same as the data received from the core. This is accomplished by monitoring the RDat and RCtl signals that are input into the Sink core, and comparing them to the TCtl and TDat signals output from the Source core. This is a simple comparison as long as the data being sent does not violate the OIF-SPI4-02.1specification. If the specification is violated, the SPI-4.2 core modifies the data to enforce compliance, and the data monitor accounts for the modification before comparing TDat to RDat. In addition to the data, the monitor also verifies DIP4, SOP spacing, IDLE request, Training request, DATA_MAX_T, and ALPHA_DATA compliance. Changes in the testcase can create situations that cause the data monitor to output warning messages. For more information on output warning messages, see Appendix C, “Data and Status Monitor Warnings.”

Status Monitor

The status monitor inspects the RStat bus. In addition to verifying correct values for channel status, it compiles the current status for each channel into the vector FullVec. FullVec is used by the testcase module when the CHECK_RSTAT constant is set to stall data on RDat when the targeted channel is full. See Table 4-11for more information about the FullVec vector.

The status monitor also calculates the DIP2 value for RStat and compares it with what is actually received. If there is an error, it looks at the signal SnkDIP2ErrRequest to see if it was asserted and the error is expected.

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

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Contents LogiCORE IP SPI-4.2 Core UG154 March 24SPI-4.2 v8.5 Getting Started Guide Revision History Date Version RevisionSPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details Schedule of Figures 1Core Customization GUI Main WindowSPI-4.2 v8.5 Getting Started Guide Schedule of Tables Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2SPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Preface About This Guide TypographicalOnline Document Convention Meaning or Use ExampleAbout the Core IntroductionSystem Requirements Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support CoreLicense Options Licensing the CoreBefore you Begin Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview Quick Start Example Design 1Core Customization GUI Main WindowRunning the Simulation Setting up for SimulationImplementing the Example Design Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Detailed Example Design Project directoryDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design Component name/implement 5Implement Directory Name DescriptionComponent name/simulation Directory and File ContentsImplement/results 6Results Directory Name DescriptionSimulation/functional 8Functional Directory Name DescriptionImplementation and Simulation Scripts Implementation and Simulation ScriptsSimulation/timing 9Timing Directory Name DescriptionExample Design Configuration Simulation Script DetailsBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Demonstration Test Bench ConnectionsClock Generator Demonstration Test Bench4Startup State Diagram Startup ModuleStimulus Module Calendar LoaderStatus Monitor Procedures ModuleData Monitor Test Case Package Constant Default Value DescriptionCustomizing the Demonstration Test Bench 10Testcase Package User-Defined ConstantsTestdatafile Constant Default Value Description Type Range Testcase Module11Useful Testcase Signals Name Description 12Testcase Module Request Signals Name FunctionCalendar Sequence Files Sink and Source Detailed Example Design Procedures Module Vhdl DetailsTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Appendix B Verilog Details Table B-3sendidles cycles Inputs Name Range DescriptionRandom Testcase Sample Code Table B-7getstatus channel Inputs Range DescriptionAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings Timing Simulation Warning and Error Messages SETUP, HOLD, Recovery violation on /XFFAppendix D Timing Simulation Warning and Error Messages

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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