Xilinx UG154 manual Example Design Configuration, Simulation Script Details

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Chapter 4: Detailed Example Design

If the core was generated with the Full System Hardware Evaluation or the Full license, the implementation script is present and performs the following steps:

1.Synthesizes the example design using the selected synthesis tool (XST or Synplify).

2.Runs ngdbuild to consolidate the core netlists, wrapper netlist, and constraints file into the common database.

3.Runs map to perform technology specific mapping of the design.

4.Runs par to perform place and route of the design.

5.Runs trce to perform static timing analysis of the routed design.

6.Runs bitgen to generate a bitstream for download to the target FPGA.

7.Runs netgen to generate a post-par simulation model for use in timing simulation.

Simulation Script Details

The simulation scripts for ModelSim and NCSIM that simulate the demonstration test bench are located in one of the following directories:

<proj_dir>/<component_name>/simulation/{functional timing }/

For functional simulation, the simulation script performs the following tasks:

1.Compiles the simulation models provided with the core.

2.Compiles the loopback example design.

3.Compiles the wrapper file, which instantiates the cores and the loopback.

4.Compiles the demonstration test bench.

5.Starts a simulation of the demonstration test bench.

6.Opens the waveform viewer and adds key signals (wave_mti.dowave_ncsim.sv).

7.Runs the simulation.

For timing simulation, the simulation script performs the following tasks:

1.Compiles the post-par design example, which includes the cores and the loopback.

2.Compiles the demonstration test bench.

3.Starts a simulation of the demonstration test bench.

4.Opens the waveform viewer and adds key signals (wave_mti.dowave_ncsim.sv).

5.Runs the simulation.

Example Design Configuration

In the example design, a Loopback Module is connected to the user interface of the SPI-4.2 core. Typically, the user interface would be connected directly to the design. The SPI-4.2 Interface, which is the interface defined by the OIF-SPI4-02.1specification, typically

32	www.xilinx.com	SPI-4.2 v8.5 Getting Started Guide
		UG154 March 24, 2008

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Contents LogiCORE IP SPI-4.2 Core UG154 March 24SPI-4.2 v8.5 Getting Started Guide Revision History Date Version RevisionSPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details Schedule of Figures 1Core Customization GUI Main WindowSPI-4.2 v8.5 Getting Started Guide Schedule of Tables Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2SPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Typographical Online DocumentPreface About This Guide Convention Meaning or Use ExampleIntroduction System RequirementsAbout the Core Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback CoreLicensing the Core Before you BeginLicense Options Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview Quick Start Example Design 1Core Customization GUI Main WindowSetting up for Simulation Implementing the Example DesignRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Detailed Example Design Project directoryDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design Component name/implement 5Implement Directory Name Description Directory and File Contents Implement/results Component name/simulation 6Results Directory Name DescriptionSimulation/functional 8Functional Directory Name DescriptionImplementation and Simulation Scripts Simulation/timingImplementation and Simulation Scripts 9Timing Directory Name DescriptionExample Design Configuration Simulation Script DetailsBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Demonstration Test Bench ConnectionsClock Generator Demonstration Test Bench4Startup State Diagram Startup ModuleStimulus Module Calendar LoaderStatus Monitor Procedures ModuleData Monitor Constant Default Value Description Customizing the Demonstration Test BenchTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Constant Default Value Description Type Range Testcase Module11Useful Testcase Signals Name Description 12Testcase Module Request Signals Name FunctionCalendar Sequence Files Sink and Source Detailed Example Design Procedures Module Vhdl DetailsTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Appendix B Verilog Details Table B-3sendidles cycles Inputs Name Range DescriptionRandom Testcase Sample Code Table B-7getstatus channel Inputs Range DescriptionAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings Timing Simulation Warning and Error Messages SETUP, HOLD, Recovery violation on /XFFAppendix D Timing Simulation Warning and Error Messages