Xilinx UG154 manual Testcase Module, Constant Default Value Description Type Range

Page 41

Demonstration Test Bench

Table 4-10:Testcase Package User-Defined Constants (Continued)

R

Name

Constant

Default Value

Description

Type

(Range)

 

 

 

 

 

 

DATA_NUM_TRAIN_SEQ

Integer

3 <0 - 255>

Sets the number of complete training patterns that

 

 

 

the demonstration test bench has to receive on

 

 

 

TDat (upon startup) before it stops sending

 

 

 

framing sequences on TStat. Once this happens,

 

 

 

the demonstration test bench begins sending

 

 

 

valid status.

 

 

 

 

TDCLK_PERIOD

Time

2.86 ns

Sets the period of the SysClk signal, which is used

 

 

<time>

by the Source core to generate TDClk. Value must

 

 

be greater than or equal to 2.00 ns (≤ 500 MHz).

 

 

 

 

 

 

 

RDCLK_PERIOD

Time

2.86 ns

Sets the period of the RDClk signal and the half-

 

 

<time>

period of the RDClk2x signal. Value must be

 

 

greater than or equal to 2.00 ns (≤ 500 MHz).

 

 

 

 

 

 

 

USERCLK_PERIOD

Time

5.71 ns

Sets the period of the UserClk, used for the

 

 

<time>

loopback interface to the cores and programming

 

 

of the calendars. Value must be greater than or

 

 

 

 

 

 

equal to 4.00 ns (≤ 250 MHz).

 

 

 

 

TFF

Time

500 ps

Clock-to-out time used by logic in the

 

 

<time>

demonstration test bench

 

 

 

 

 

 

 

Testcase Module

The testcase module generates data and sends it to the stimulus module, which in turn transmits data to the Sink core and status to the Source core. The following data is created in the testcase module:

•Static configuration signals

•SPI-4.2 and demonstration test bench requests

•Source core status and Sink core data

Figure 4-2shows the interface between the testcase and stimulus modules.

The static configuration signals are set when the SPI-4.2 core is generated; these signals can also be modified in circuit. The description of these signals can be found in the SPI-4.2 Core User Guide.

The status and data generation is simplified by instantiating the procedures module and calling the functions contained in the module. This allows the testcase module to be completely asynchronous, as all of the clocking is done in the procedures module.

SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Online Document TypographicalPreface About This Guide Convention Meaning or Use ExampleSystem Requirements IntroductionAbout the Core Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreBefore you Begin Licensing the CoreLicense Options Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview 1Core Customization GUI Main Window Quick Start Example DesignImplementing the Example Design Setting up for SimulationRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design 5Implement Directory Name Description Component name/implementImplement/results Directory and File ContentsComponent name/simulation 6Results Directory Name Description8Functional Directory Name Description Simulation/functionalSimulation/timing Implementation and Simulation ScriptsImplementation and Simulation Scripts 9Timing Directory Name DescriptionSimulation Script Details Example Design ConfigurationBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleStatus Monitor Procedures ModuleData Monitor Customizing the Demonstration Test Bench Constant Default Value DescriptionTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

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Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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