Xilinx UG154 manual Customizing the Demonstration Test Bench, Test Case Package, Range

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Demonstration Test Bench

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Lastly, the signal SnkInFrame is created in the status monitor by inverting SnkOof. This signal is used by the stimulus module to send training. See Appendix C, “Data and Status Monitor Warnings.”

Customizing the Demonstration Test Bench

The demonstration test bench can be used with default settings or customized to observe the behavior of the SPI-4.2 core for different configurations.

The demonstration test bench can be programmed to transmit a range of stimuli by modifying TSCLK_LCK.

•Testcase Package—contains constants used by the testcase module

•Testcase Module—generates data and status

•Sink Calendar Sequence—contains the channel order for the Sink core status

•Source Calendar Sequence—contains the channel order for the Source core status

The following sections describe each module, including customization methods and resulting behavior. The module descriptions are applicable to both VHDL and Verilog designs. Language-specific details for VHDL are provided in Appendix A, “VHDL Details.” Language-specific details and source code showing how to further randomize input to the SPI-4.2 core for Verilog are provided in Appendix B, “Verilog Details.”

Test Case Package

The test case package contains a list of constants that define the ways that the cores and demonstration test bench operate. Some of these are user-defined and can be modified, while others are defined when the core is generated. Table 4-10provides test bench constants that can be modified. These constants are modified by regenerating the core in the CORE Generator system.

Table 4-10:Testcase Package User-Defined Constants

Name

Constant

Default Value

Description

Type

(Range)

 

 

 

 

 

 

SNK_CAL_DATA

String

snk_calendar.dat

Contains the name of the file with the Sink

 

 

<filename>

calendar sequence to be programmed.

 

 

 

 

 

 

 

SRC_CAL_DATA

String

src_calendar.dat

Contains the name of the file with the Source

 

 

<filename>

calendar sequence to be programmed.

 

 

 

 

 

 

 

SNK_ALPHA_DATA

Integer

3 <0 - 255>

Sets the number of repetitions of the 20-word

 

 

 

training pattern sent to the Sink core (0 means

 

 

 

don’t send periodic training).

 

 

 

 

SNK_DATA_MAX_T

Integer

4000 <0-65535>

Sets the number of cycles between training

 

 

 

patterns sent to the Sink core (0 means don’t send

 

 

 

periodic training).

 

 

 

 

SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Contents About This GuideConventions Convention Meaning or Use Example TypographicalOnline Document Preface About This GuideRecommended Design Experience IntroductionSystem Requirements About the CoreCore Additional Core ResourcesTechnical Support FeedbackSimulation-Only Evaluation Licensing the CoreBefore you Begin License OptionsObtaining Your License FullLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Quick Start Example Design OverviewGenerating the Core 1Core Customization GUI Main Window Quick Start Example DesignFunctional Simulation Setting up for SimulationImplementing the Example Design Running the SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents Directory and File Contents 3Doc Directory Component name/example design4Example Design Directory Name Description 5Implement Directory Name Description Component name/implement6Results Directory Name Description Directory and File ContentsImplement/results Component name/simulation8Functional Directory Name Description Simulation/functional9Timing Directory Name Description Implementation and Simulation ScriptsSimulation/timing Implementation and Simulation ScriptsSimulation Script Details Example Design ConfigurationExample Design Configuration Loopback ModuleBasic Loopback Operation Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock Generator Startup Module 4Startup State DiagramCalendar Loader Stimulus ModuleProcedures Module Data MonitorStatus Monitor 10Testcase Package User-Defined Constants Constant Default Value DescriptionCustomizing the Demonstration Test Bench Test Case PackageTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages
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