Xilinx UG154 manual Appendix a Vhdl Details

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Appendix A: VHDL Details

48	www.xilinx.com	SPI-4.2 v8.5 Getting Started Guide
		UG154 March 24, 2008

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Contents LogiCORE IP SPI-4.2 Core UG154 March 24SPI-4.2 v8.5 Getting Started Guide Revision History Date Version RevisionSPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details Schedule of Figures 1Core Customization GUI Main WindowSPI-4.2 v8.5 Getting Started Guide Schedule of Tables Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2SPI-4.2 v8.5 Getting Started Guide Contents About This GuideConventions Typographical Online DocumentPreface About This Guide Convention Meaning or Use ExampleIntroduction System RequirementsAbout the Core Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback CoreLicensing the Core Before you BeginLicense Options Simulation-Only EvaluationObtaining Your License FullLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Quick Start Example Design OverviewGenerating the Core Quick Start Example Design 1Core Customization GUI Main WindowSetting up for Simulation Implementing the Example DesignRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Detailed Example Design Project directoryDirectory and File Contents Directory and File Contents 3Doc Directory Component name/example design4Example Design Directory Name Description Component name/implement 5Implement Directory Name DescriptionDirectory and File Contents Implement/resultsComponent name/simulation 6Results Directory Name DescriptionSimulation/functional 8Functional Directory Name DescriptionImplementation and Simulation Scripts Simulation/timingImplementation and Simulation Scripts 9Timing Directory Name DescriptionExample Design Configuration Simulation Script DetailsExample Design Configuration Loopback ModuleBasic Loopback Operation Demonstration Test Bench Demonstration Test Bench ConnectionsClock Generator Demonstration Test Bench4Startup State Diagram Startup ModuleStimulus Module Calendar LoaderProcedures Module Data MonitorStatus Monitor Constant Default Value Description Customizing the Demonstration Test BenchTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Constant Default Value Description Type Range Testcase Module11Useful Testcase Signals Name Description 12Testcase Module Request Signals Name FunctionCalendar Sequence Files Sink and Source Detailed Example Design Procedures Module Vhdl DetailsTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Appendix B Verilog Details Table B-3sendidles cycles Inputs Name Range DescriptionRandom Testcase Sample Code Table B-7getstatus channel Inputs Range DescriptionAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings Timing Simulation Warning and Error Messages SETUP, HOLD, Recovery violation on /XFFAppendix D Timing Simulation Warning and Error Messages