Xilinx UG154 manual Installing Your License File

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Installing Your License File

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Follow the instructions in the lounge to fill out the license request form; then click Submit to automatically generate the license. An email containing the license and installation instructions will be sent to you immediately.

Installing Your License File

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SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Online Document TypographicalPreface About This Guide Convention Meaning or Use ExampleSystem Requirements IntroductionAbout the Core Recommended Design Experience Technical Support Additional Core Resources Feedback CoreBefore you Begin Licensing the CoreLicense Options Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview 1Core Customization GUI Main Window Quick Start Example DesignImplementing the Example Design Setting up for SimulationRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design 5Implement Directory Name Description Component name/implementImplement/results Directory and File ContentsComponent name/simulation 6Results Directory Name Description8Functional Directory Name Description Simulation/functionalSimulation/timing Implementation and Simulation ScriptsImplementation and Simulation Scripts 9Timing Directory Name DescriptionSimulation Script Details Example Design ConfigurationBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleStatus Monitor Procedures ModuleData Monitor Customizing the Demonstration Test Bench Constant Default Value DescriptionTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages