Xilinx UG154 manual Table A-3sendidles PBr, cycles Inputs Name Range Description

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R

Appendix A: VHDL Details

automatically calculated from the number of bytes sent. ERR has a higher priority than EOP; if EOP and ERR are both ‘1’, the EOPs for the burst is an EOP abort = ‘01’.

Table A-2:send_user_data (PBr, SOP, EOP, Err, Addr, bytes) Inputs

Name

Range

Description

 

 

 

SOP

0 or 1

Defines if the packet should begin with a SOP.

 

 

 

EOP

0 or 1

Defines if the packet should be terminated with

 

 

an EOP.

 

 

 

ERR

0 or 1

Defines if the packet should be terminated with

 

 

an EOP abort.

 

 

 

ADDR

0 to 255

Channel on which the packet should be sent.

 

 

 

BYTES

1 to 255

Number of bytes to send on the selected channel.

 

 

 

The send_idles procedure is used to send idle control words.

Table A-3:send_idles (PBr, cycles) Inputs

Name

Range

Description

 

 

 

CYCLES

0 to 511

Number of idle control words to send on RDat.

 

 

 

The send_training procedure is used to send training patterns.

Table A-4:send_training (PBr, patterns) Inputs

Name

Range

Description

 

 

 

PATTERNS

0 to 255

Number of training patterns to send.

 

 

 

The sop_spacing procedure is used to send errored data by sending two SOPs in less than eight cycles. This function limits the number of cycles between the two SOPs to less than seven. This ensures that a SOP spacing error occurs.

Table A-5:sop_spacing (PBr, Bytes1, Err1, Addr1, EOP2, Err2, Addr2, Bytes2, num_cycles) Inputs

Name

Range

Description

 

 

 

BYTES1

0 to 10

The number of bytes to send in the first burst.

 

 

This is limited to 10 bytes to ensure SOP spacing

 

 

is violated.

 

 

 

ERR1

0 or 1

Defines if the first packet should be terminated

 

 

with an EOP abort. If set to 0 the EOPs will be

 

 

calculated from BYTES1.

 

 

 

ADDR1

0 to 255

Channel on which the first packet should be sent.

 

 

 

EOP2

0 or 1

Defines if the second packet should be

 

 

terminated with an EOP.

 

 

 

ERR2

0 or 1

Defines if the second packet should be

 

 

terminated with an EOP abort. If set to 0 the

 

 

EOPs will be calculated from Bytes1.

 

 

 

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

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Contents LogiCORE IP SPI-4.2 Core UG154 March 24SPI-4.2 v8.5 Getting Started Guide Revision History Date Version RevisionSPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details Schedule of Figures 1Core Customization GUI Main WindowSPI-4.2 v8.5 Getting Started Guide Schedule of Tables Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2SPI-4.2 v8.5 Getting Started Guide About This Guide ContentsConventions Preface About This Guide TypographicalOnline Document Convention Meaning or Use ExampleAbout the Core IntroductionSystem Requirements Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support CoreLicense Options Licensing the CoreBefore you Begin Simulation-Only EvaluationFull Obtaining Your LicenseLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Overview Quick Start Example DesignGenerating the Core Quick Start Example Design 1Core Customization GUI Main WindowRunning the Simulation Setting up for SimulationImplementing the Example Design Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Detailed Example Design Project directoryDirectory and File Contents Component name/example design Directory and File Contents 3Doc Directory4Example Design Directory Name Description Component name/implement 5Implement Directory Name DescriptionComponent name/simulation Directory and File ContentsImplement/results 6Results Directory Name DescriptionSimulation/functional 8Functional Directory Name DescriptionImplementation and Simulation Scripts Implementation and Simulation ScriptsSimulation/timing 9Timing Directory Name DescriptionExample Design Configuration Simulation Script DetailsLoopback Module Example Design ConfigurationBasic Loopback Operation Demonstration Test Bench Demonstration Test Bench ConnectionsClock Generator Demonstration Test Bench4Startup State Diagram Startup ModuleStimulus Module Calendar LoaderData Monitor Procedures ModuleStatus Monitor Test Case Package Constant Default Value DescriptionCustomizing the Demonstration Test Bench 10Testcase Package User-Defined ConstantsTestdatafile Constant Default Value Description Type Range Testcase Module11Useful Testcase Signals Name Description 12Testcase Module Request Signals Name FunctionCalendar Sequence Files Sink and Source Detailed Example Design Procedures Module Vhdl DetailsTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Appendix B Verilog Details Table B-3sendidles cycles Inputs Name Range DescriptionRandom Testcase Sample Code Table B-7getstatus channel Inputs Range DescriptionAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings Timing Simulation Warning and Error Messages SETUP, HOLD, Recovery violation on /XFFAppendix D Timing Simulation Warning and Error Messages

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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