Xilinx UG154 manual Random Testcase Sample Code

Page 53

Random Testcase Sample Code

R

begin

if (DIP4RequestCnt > 0) begin

DIP4RequestCnt <= DIP4RequestCnt - 1'b1; TCDIP4Request <= 1'b1;

end else begin

DIP4RequestCnt <= 'b0; TCDIP4Request <= 1'b0;

end end else begin

TCDIP4Request <= 1'b1;

DIP4RequestCnt <= {$random(`RANDOM_SEED + $time)} % 9; end

end

//Randomly set TCDIP2Request to 1

if ((RandDIP2Request == 0) (TCDIP2Request == 1)) begin

if (TCDIP2Request == 1) begin

if (DIP2RequestCnt > 0) begin

DIP2RequestCnt <= DIP2RequestCnt - 1'b1; TCDIP2Request <= 1'b1;

end else begin

DIP2RequestCnt <= 'b0; TCDIP2Request <= 1'b0;

end end else begin

TCDIP2Request <= 1'b1;

DIP2RequestCnt <= {$random(`RANDOM_SEED + $time)} % 9; end

end

//Randomly set TCSnkDip2ErrRequest to 1

if ((RandSnkDip2ErrRequest == 0) (TCSnkDip2ErrRequest == 1)) begin

if (TCSnkDip2ErrRequest == 1) begin

if (SnkDip2ErrRequestCnt > 0) begin

SnkDip2ErrRequestCnt <= SnkDip2ErrRequestCnt - 1'b1; TCSnkDip2ErrRequest <= 1'b1;

end else begin

SnkDip2ErrRequestCnt <= 'b0; TCSnkDip2ErrRequest <= 1'b0;

end end else

SPI-4.2 v8.5 Getting Started Guide

www.xilinx.com

53

UG154 March 24, 2008

Image 53

Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Online Document TypographicalPreface About This Guide Convention Meaning or Use ExampleSystem Requirements IntroductionAbout the Core Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreBefore you Begin Licensing the CoreLicense Options Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview 1Core Customization GUI Main Window Quick Start Example DesignImplementing the Example Design Setting up for SimulationRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design 5Implement Directory Name Description Component name/implementImplement/results Directory and File ContentsComponent name/simulation 6Results Directory Name Description8Functional Directory Name Description Simulation/functionalSimulation/timing Implementation and Simulation ScriptsImplementation and Simulation Scripts 9Timing Directory Name DescriptionSimulation Script Details Example Design ConfigurationBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleStatus Monitor Procedures ModuleData Monitor Customizing the Demonstration Test Bench Constant Default Value DescriptionTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages