Xilinx UG154 manual Implementation and Simulation Scripts, Simulation/timing

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Implementation and Simulation Scripts

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simulation/timing

The timing directory contains timing simulation scripts provided with the core.

Table 4-9:Timing Directory

Name	Description

<project_dir>/<component_name>/simulation/timing

simulate_mti.do	ModelSim macro file that compiles the
	post-par timing netlist and demo HDL
	source. The script also loads and runs the
	simulation for 8 μs. The implement script
	must first be run to generate the post-par
	timing simulation model. Simulation can
	only be run after the timing simulation
	model is generated.

wave_mti.do	ModelSim macro file that opens a wave
	window and adds key signals to the wave
	viewer. The wave_mti.do file is called by
	the simulate_mti.do macro file.

simulate_ncsim.sh	Shell scripts that compile the functional
simulate_ncsim.bat	netlist and loopback HDL source. The
	script also launches NCSIM and runs the
	simulation for 8 μs.

wave_ncsim.sv	A NCSIM macro file that opens a wave
	window and adds key signals to the wave
	viewer. The wave_ncsim.sv file is called by
	the simulate_ncsim.sh or
	simulate_ncsim.bat file.

simulate_vcs.sh (verilog only)	Shell script that compiles the structural
	netlist and example design. The script also
	runs the functional simulation using VCS.

vcs_session.tcl (verilog only)	VCS tcl script that opens a wave window.
	This macro is called by the simulate_vcs.sh
	script.

vcs_commands.key (verilog only)	VCS command file. This file is called by the
	simulate_vcs.sh script.

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Implementation and Simulation Scripts

The implementation script is either a shell script or a batch file that runs the example design through the Xilinx tool flow. The scripts are located in the following directory:

<proj_dir>/<component_name>/implement/

The implementation scripts are parameterized based on the Design Entry Tool and Design Entry Language CORE Generator project options. If either of these project options are changed, the core must be regenerated to create the appropriate implementation scripts.

SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide About This Guide ContentsConventions Convention Meaning or Use Example TypographicalOnline Document Preface About This GuideRecommended Design Experience IntroductionSystem Requirements About the CoreCore Additional Core ResourcesTechnical Support FeedbackSimulation-Only Evaluation Licensing the CoreBefore you Begin License OptionsFull Obtaining Your LicenseLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Overview Quick Start Example DesignGenerating the Core 1Core Customization GUI Main Window Quick Start Example DesignFunctional Simulation Setting up for SimulationImplementing the Example Design Running the SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents Component name/example design Directory and File Contents 3Doc Directory4Example Design Directory Name Description 5Implement Directory Name Description Component name/implement6Results Directory Name Description Directory and File ContentsImplement/results Component name/simulation8Functional Directory Name Description Simulation/functional9Timing Directory Name Description Implementation and Simulation ScriptsSimulation/timing Implementation and Simulation ScriptsSimulation Script Details Example Design ConfigurationLoopback Module Example Design ConfigurationBasic Loopback Operation Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleData Monitor Procedures ModuleStatus Monitor 10Testcase Package User-Defined Constants Constant Default Value DescriptionCustomizing the Demonstration Test Bench Test Case PackageTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages