Xilinx UG154 manual Stimulus Module, Calendar Loader

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Demonstration Test Bench

R

•RDCLK_RST Holds DCMReset_RDClk for 8 cycles then releases it

•RDCLK_LCK Waits for the Locked_RDClk signal.

•TSCLK_RST Holds DCMReset_TSClk for 12 cycles then releases it.

•TSCLK_LCK Waits for the Locked_TSClk signal.

•CLKS_RDY Waits for SnkClksRdy and SrcClksRdy signals.

•RELEASE_RST Releases Reset_n.

Calendar Loader

The second function of the Startup module is the logic to load the calendars. The demonstration test bench reads the Sink calendar sequence and the Source calendar sequence from two different files and loads this information into the calendars of the Sink and Source cores and into the Stimulus module. It also loads the calendar into the Status Monitor so that it can identify which channel is receiving status. The calendar sequences can be modified (see “Calendar Sequence Files (Sink and Source),” page 43).

DPA Initialization

The third function of the Startup module is to initialize the Dynamic Phase Alignment section of the Sink core. It is present in the module only if Dynamic Alignment is selected in the CORE Generator system. It simply asserts the PhaseAlignRequest signal to the Sink core for two cycles of UserClk once the core is out of reset.

Once PhaseAlignRequest is asserted, the dynamic alignment algorithm needs some time before completing its alignment and asserting PhaseAlignComplete. This value is dependent on the frequency of RDClk and when PhaseAlignRequest is asserted.

Stimulus Module

While the testcase and procedures modules are used to generate data and status, the stimulus module is used to actually send this data to the SPI-4.2 core. The stimulus module either transmits data and status generated by the testcase module, or it directly transmits training or idle data and framing status. In addition to sending status and data, the stimulus module drives the static configuration signals defined in the testcase module. The behavior of the stimulus module can be modified with the constants defined in the testcase package.

The Stimulus module also performs the following operations:

•Sends training or framing if the core is out of frame

•Inserts periodic training on RDat

•Ensures minimum SOP spacing is met

•Calculates DIP2 and DIP4 values

•Drives Source core request signals

•Merges SOP and EOP control words

The Stimulus module has two status inputs: SnkInFrame and SrcInFrame. If SnkInFrame is deasserted, the stimulus module sends training patterns over RDat until SnkInFrame is asserted. If SrcInFrame is deasserted, the stimulus module sends framing over TStat until SrcInFrame is asserted.

SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide About This Guide ContentsConventions Online Document TypographicalPreface About This Guide Convention Meaning or Use ExampleSystem Requirements IntroductionAbout the Core Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreBefore you Begin Licensing the CoreLicense Options Simulation-Only EvaluationFull Obtaining Your LicenseLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Overview Quick Start Example DesignGenerating the Core 1Core Customization GUI Main Window Quick Start Example DesignImplementing the Example Design Setting up for SimulationRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents Component name/example design Directory and File Contents 3Doc Directory4Example Design Directory Name Description 5Implement Directory Name Description Component name/implementImplement/results Directory and File ContentsComponent name/simulation 6Results Directory Name Description8Functional Directory Name Description Simulation/functionalSimulation/timing Implementation and Simulation ScriptsImplementation and Simulation Scripts 9Timing Directory Name DescriptionSimulation Script Details Example Design ConfigurationLoopback Module Example Design ConfigurationBasic Loopback Operation Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleData Monitor Procedures ModuleStatus Monitor Customizing the Demonstration Test Bench Constant Default Value DescriptionTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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