Xilinx UG154 manual Clock Generator, Demonstration Test Bench

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Demonstration Test Bench

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•	Status Monitor
•	Testcase
		Demonstration Testbench
	Clock
	Generator
	Data
	Monitor	SrcInFrame
		Static Config. Signals	Testcase
		TCDat	Testcase
		TCDat	Package
			Package
		TCCtl
		FFWriteEn
		SopErr
		TCStat
	Stimulus	TCChan	Testcase
	Stimulus	TCIdleRequest	Testcase
	Module	TCIdleRequest	Module
	Module		Module
		TCTrainingRequest
		TCSinkDip2ErrRequest
		TCDIP2Request
		CtlFull
		GetStatusChan
		GetStatus
			Procedures
		FullVec
	Status	SnkInFrame
	Status
	Monitor
	Figure 4-3:Test Bench Modules

Clock Generator

The Clock Generator creates all of the clocks that are used in the Design Example, including SysClk, RDClk2x, UserClk, TSClk, and SnkIdelayRefClk. These clocks are described in more detail in Table 4-10.

SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Convention Meaning or Use Example TypographicalOnline Document Preface About This GuideRecommended Design Experience IntroductionSystem Requirements About the CoreCore Additional Core ResourcesTechnical Support FeedbackSimulation-Only Evaluation Licensing the CoreBefore you Begin License OptionsLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview 1Core Customization GUI Main Window Quick Start Example DesignFunctional Simulation Setting up for SimulationImplementing the Example Design Running the SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example DesignDirectory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design 5Implement Directory Name Description Component name/implement6Results Directory Name Description Directory and File ContentsImplement/results Component name/simulation8Functional Directory Name Description Simulation/functional9Timing Directory Name Description Implementation and Simulation ScriptsSimulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design ConfigurationBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleStatus Monitor Procedures ModuleData Monitor 10Testcase Package User-Defined Constants Constant Default Value DescriptionCustomizing the Demonstration Test Bench Test Case PackageTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages