Xilinx UG154 manual Implement/results, Component name/simulation, Directory and File Contents

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Directory and File Contents

R

implement/results

The results directory is created by the implement script, after which the implement script results are placed in the results directory.

Table 4-6:Results Directory

Name	Description

<project_dir>/<component_name>/implement/results

Implement script result files.

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<component name>/simulation

The simulation directory contains the necessary files to test a VHDL or Verilog example design with the demonstration test bench.

Table 4-7:Simulation Directory

Name	Description

<project_dir>/<component_name>/simulation

data_file.dat	Data file containing the data to be sent
	across the SPI-4.2 Interface

pl4_clk_gen.v[hd]	Demo Test bench Clock Generator

pl4_data_monitor.v[hd]	Demo Test bench Data Monitor

pl4_demo_testbench.v[hd]	Demo Test bench Top Level Module

pl4_procedures.v[hd]	Demo Test bench Procedures Module

pl4_src_clk.v[hd]	HDL file which is utilized if the Slave core
	is configured with slave clocking

pl4_startup.v[hd]	Demo Test bench DCM Startup and
	Calendar Loader Module

pl4_status_monitor.v[hd]	Demo Test bench Status Monitor

pl4_stimulus.v[hd]	Demo Test bench Data and Status Stimulus
	Module

pl4_testcase.v[hd]	Controls the operation of the demonstration
pl4_testcase_pkg.v[hd]	test bench and can be user-modified.

snk_calendar.dat	Data file containing the calendar
	information for the Sink interface

src_calendar.dat	Data file containing the calendar
	information for the Source interface

[glbl.v]	Asserts initial global reset pulse
	(Verilog only)

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SPI-4.2 v8.5 Getting Started Guide

www.xilinx.com

29

UG154 March 24, 2008

Image 29

Contents UG154 March 24 LogiCORE IP SPI-4.2 CoreSPI-4.2 v8.5 Getting Started Guide Date Version Revision Revision HistorySPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details 1Core Customization GUI Main Window Schedule of FiguresSPI-4.2 v8.5 Getting Started Guide Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2 Schedule of TablesSPI-4.2 v8.5 Getting Started Guide Conventions ContentsAbout This Guide Online Document TypographicalPreface About This Guide Convention Meaning or Use ExampleSystem Requirements IntroductionAbout the Core Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreBefore you Begin Licensing the CoreLicense Options Simulation-Only EvaluationLicensing the Core Obtaining Your LicenseFull Installing Your License File Installing Your License FileLicensing the Core Generating the Core Quick Start Example DesignOverview 1Core Customization GUI Main Window Quick Start Example DesignImplementing the Example Design Setting up for SimulationRunning the Simulation Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Project directory Detailed Example Design Directory and File Contents 4Example Design Directory Name Description Directory and File Contents 3Doc DirectoryComponent name/example design 5Implement Directory Name Description Component name/implementImplement/results Directory and File ContentsComponent name/simulation 6Results Directory Name Description8Functional Directory Name Description Simulation/functionalSimulation/timing Implementation and Simulation ScriptsImplementation and Simulation Scripts 9Timing Directory Name DescriptionSimulation Script Details Example Design ConfigurationBasic Loopback Operation Example Design ConfigurationLoopback Module Demonstration Test Bench Connections Demonstration Test BenchDemonstration Test Bench Clock GeneratorStartup Module 4Startup State DiagramCalendar Loader Stimulus ModuleStatus Monitor Procedures ModuleData Monitor Customizing the Demonstration Test Bench Constant Default Value DescriptionTest Case Package 10Testcase Package User-Defined ConstantsTestdatafile Testcase Module Constant Default Value Description Type Range12Testcase Module Request Signals Name Function 11Useful Testcase Signals Name DescriptionCalendar Sequence Files Sink and Source Detailed Example Design Vhdl Details Procedures ModuleTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Table B-3sendidles cycles Inputs Name Range Description Appendix B Verilog DetailsTable B-7getstatus channel Inputs Range Description Random Testcase Sample CodeAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings SETUP, HOLD, Recovery violation on /XFF Timing Simulation Warning and Error MessagesAppendix D Timing Simulation Warning and Error Messages