Xilinx
UG154
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Appendix D Timing Simulation Warning and Error Messages
Install
4Startup State Diagram
Example Design Configuration
Setting up for Simulation
Procedures Module
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Appendix D:
Timing Simulation Warning and Error Messages
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SPI-4.2
v8.5 Getting Started Guide
UG154 March 24, 2008
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Contents
LogiCORE IP SPI-4.2 Core
UG154 March 24
SPI-4.2 v8.5 Getting Started Guide
Revision History
Date Version Revision
SPI-4.2 v8.5 Getting Started Guide
Table of Contents
Appendix a Vhdl Details
Schedule of Figures
1Core Customization GUI Main Window
SPI-4.2 v8.5 Getting Started Guide
Schedule of Tables
Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2
SPI-4.2 v8.5 Getting Started Guide
About This Guide
Contents
Conventions
Preface About This Guide
Typographical
Online Document
Convention Meaning or Use Example
About the Core
Introduction
System Requirements
Recommended Design Experience
Feedback
Additional Core Resources
Technical Support
Core
License Options
Licensing the Core
Before you Begin
Simulation-Only Evaluation
Full
Obtaining Your License
Licensing the Core
Installing Your License File
Installing Your License File
Licensing the Core
Overview
Quick Start Example Design
Generating the Core
Quick Start Example Design
1Core Customization GUI Main Window
Running the Simulation
Setting up for Simulation
Implementing the Example Design
Functional Simulation
Timing Simulation
Running the Simulation
Quick Start Example Design
Detailed Example Design
Project directory
Directory and File Contents
Component name/example design
Directory and File Contents 3Doc Directory
4Example Design Directory Name Description
Component name/implement
5Implement Directory Name Description
Component name/simulation
Directory and File Contents
Implement/results
6Results Directory Name Description
Simulation/functional
8Functional Directory Name Description
Implementation and Simulation Scripts
Implementation and Simulation Scripts
Simulation/timing
9Timing Directory Name Description
Example Design Configuration
Simulation Script Details
Loopback Module
Example Design Configuration
Basic Loopback Operation
Demonstration Test Bench
Demonstration Test Bench Connections
Clock Generator
Demonstration Test Bench
4Startup State Diagram
Startup Module
Stimulus Module
Calendar Loader
Data Monitor
Procedures Module
Status Monitor
Test Case Package
Constant Default Value Description
Customizing the Demonstration Test Bench
10Testcase Package User-Defined Constants
Testdatafile
Constant Default Value Description Type Range
Testcase Module
11Useful Testcase Signals Name Description
12Testcase Module Request Signals Name Function
Calendar Sequence Files Sink and Source
Detailed Example Design
Procedures Module
Vhdl Details
Table A-3sendidles PBr, cycles Inputs Name Range Description
ADDR2
Appendix a Vhdl Details
Verilog Details
Appendix B Verilog Details
Table B-3sendidles cycles Inputs Name Range Description
Random Testcase Sample Code
Table B-7getstatus channel Inputs Range Description
Appendix B Verilog Details
Random Testcase Sample Code
Appendix B Verilog Details
Data and Status Monitor Warnings
Appendix C Data and Status Monitor Warnings
Timing Simulation Warning and Error Messages
SETUP, HOLD, Recovery violation on /XFF
Appendix D Timing Simulation Warning and Error Messages
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