Xilinx UG154 manual 11Useful Testcase Signals Name Description

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Chapter 4: Detailed Example Design

Table 4-11contains a list of common useful test case signals and descriptions.

Table 4-11:Useful Testcase Signals

Name

Description

 

 

FullVec

An array of bits indicating the last status received on RStat for

 

each channel. For each channel, the corresponding bit is set (1)

 

if the status received was ‘10’ - satisfied, and cleared (0) if the

 

status was ‘01’ - hungry or ‘00’ - starving.

 

 

NumLinks

The number of channels for which the core was configured.

 

 

Reset_n

Reset signal to the Sink and Source core (active low).

 

 

SnkEn

Enable signal to the Sink core.

 

 

SnkFifoReset_n

FIFO Reset signal to the Sink core (active low).

 

 

SnkInFrame

Asserted when the Sink core is in frame (as interpreted by the

 

status monitor).

 

 

SnkOof

Out-of-Frame signal from the Sink core.

 

 

SrcEn

Enable signal to the Source core.

 

 

SrcFifoReset_n

FIFO Reset signal to the Source core (active low).

 

 

SrcInFrame

Asserted when the Source core is in frame (as interpreted by

 

the data monitor).

 

 

SrcOof

Out-of-Frame signal from the Source core.

 

 

There are five request signals that can be asserted in the testcase module. The first four signals interface to the stimulus module (see Figure 4-2, page 34). The fifth is encapsulated with the generated data sent to the stimulus module. Table 4-12details request signals.

Table 4-12:Testcase Module Request Signals

Name

Function

 

 

TCIdleRequest

Drives the IdleRequest input to the Source core, which results

 

in idles begin transmitted on TDat.

 

 

TCTrainingRequest

Drives the TrainingRequest input to the Source core, which

 

causes training to be sent on TDat.

 

 

TCSnkDip2ErrRequest

Drives the SnkDip2ErrRequest input to the Sink core, which

 

results in DIP2 errors on RStat.

 

 

TCDIP2Request

When asserted (active high), causes DIP2 errors to be

 

transmitted on TStat.

 

 

TCDIP4Request

When asserted (active high), causes DIP4 errors to be

 

transmitted on RDat.

 

 

In addition to the request signals described above, the test case module has control over the Sink and Source cores with the SnkEn, SrcEn, SnkFifoReset_n, and SrcFifoReset_n signals. Descriptions of these signals can be found in the SPI-4.2 Core User Guide.

The Source core status is also generated in the test case module using functions contained in the procedures module. Using the function send_status, you can specify a channel

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

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Contents LogiCORE IP SPI-4.2 Core UG154 March 24SPI-4.2 v8.5 Getting Started Guide Revision History Date Version RevisionSPI-4.2 v8.5 Getting Started Guide Table of Contents Appendix a Vhdl Details Schedule of Figures 1Core Customization GUI Main WindowSPI-4.2 v8.5 Getting Started Guide Schedule of Tables Table B-5sopspacing Bytes1, Err1, Addr1, EOP2, Err2, Addr2SPI-4.2 v8.5 Getting Started Guide Contents About This GuideConventions Preface About This Guide TypographicalOnline Document Convention Meaning or Use ExampleAbout the Core IntroductionSystem Requirements Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support CoreLicense Options Licensing the CoreBefore you Begin Simulation-Only EvaluationObtaining Your License FullLicensing the Core Installing Your License File Installing Your License FileLicensing the Core Quick Start Example Design OverviewGenerating the Core Quick Start Example Design 1Core Customization GUI Main WindowRunning the Simulation Setting up for SimulationImplementing the Example Design Functional SimulationTiming Simulation Running the Simulation Quick Start Example Design Detailed Example Design Project directoryDirectory and File Contents Directory and File Contents 3Doc Directory Component name/example design4Example Design Directory Name Description Component name/implement 5Implement Directory Name DescriptionComponent name/simulation Directory and File ContentsImplement/results 6Results Directory Name DescriptionSimulation/functional 8Functional Directory Name DescriptionImplementation and Simulation Scripts Implementation and Simulation ScriptsSimulation/timing 9Timing Directory Name DescriptionExample Design Configuration Simulation Script DetailsExample Design Configuration Loopback ModuleBasic Loopback Operation Demonstration Test Bench Demonstration Test Bench ConnectionsClock Generator Demonstration Test Bench4Startup State Diagram Startup ModuleStimulus Module Calendar LoaderProcedures Module Data MonitorStatus Monitor Test Case Package Constant Default Value DescriptionCustomizing the Demonstration Test Bench 10Testcase Package User-Defined ConstantsTestdatafile Constant Default Value Description Type Range Testcase Module11Useful Testcase Signals Name Description 12Testcase Module Request Signals Name FunctionCalendar Sequence Files Sink and Source Detailed Example Design Procedures Module Vhdl DetailsTable A-3sendidles PBr, cycles Inputs Name Range Description ADDR2 Appendix a Vhdl Details Verilog Details Appendix B Verilog Details Table B-3sendidles cycles Inputs Name Range DescriptionRandom Testcase Sample Code Table B-7getstatus channel Inputs Range DescriptionAppendix B Verilog Details Random Testcase Sample Code Appendix B Verilog Details Data and Status Monitor Warnings Appendix C Data and Status Monitor Warnings Timing Simulation Warning and Error Messages SETUP, HOLD, Recovery violation on /XFFAppendix D Timing Simulation Warning and Error Messages

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

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In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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