Hitachi SJ700-2 Series service manual Control board

Page 55

6-1

P

N

R

S

T

PKD

PD

SCRG

N

RB

BRDG

NN

XG

YG

ZG

UE

VE

WE

UG

VG

WG

P

U

W

OH1

THF

THP

THCOM

FF1

FF2

		Inrush current				Temp.	Fan rotation
		limit circuit			Current		Fan rotation		PV24
		limit circuit			Current		error detect		PV24
					detect (U)	error	error detect
CB circuit					detect (U)	detect	(CM1)		CM1
						detect
		Thyristo r drive				Current
	Inst. power	Thyristo r drive	BRD drive circuit	Lower arm dri ve circuit	Upper arm driv e circuit	Current
Phase fail detect	Inst. power	circuit	BRD drive circuit	Lower arm dri ve circuit	Upper arm driv e circuit	detect
Phase fail detect	failure detect	circuit	(suppress cir cuit)	(suppress cir cuit)	(suppress cir cuit)	(W)		UV detect	R0
	failure detect	(incl. suppress ci rcuit)	(suppress cir cuit)	(suppress cir cuit)	(suppress cir cuit)	(W)	Power supply	UV detect	R0
		(incl. suppress ci rcuit)					Power supply		T0
							for GA (5V)

Opt

Opt

Opt

Opt

Power supply

Opt

Opt

Power supply

Inst. power

coupler

coupler

coupler

coupler

coupler

coupler

Power

Power

Power

Power supply

for THY gate

for IGBT

failure detect

(5V)

lower arms

supply for

supply for

supply for

Power supply for

for control

Power supply

IGBT upper

IGBT upper

IGBT upper

control (+-12V)

for I/F (24V)

(PV15)

(5V)

arm (U)

arm (V)

arm (W)

Opt

Opt

coupler

coupler

RPHF

RPHF

RPHF

IPL

SCR

BRD

STR

GX

GY

GZ

GS0

GU

GV

GW

UN

VN

WN

P

IUF

IWF

PV12

L

NV12

OH

PV5

L

PV5N

PV24

CM1

FAN

UV

IPL

(N)

(N)

(N)

(N)

(N)

(L)

(N)

(N)

(N)

(N)

(N)

(N)

(N)

(N)

(N)

(N)

(N)

(N)

(L)

(L)

(L)

(L)

(L)

(N)

(L)

(L)

(N)

(CM1) (CM1)

(N)

(N)

(L)

Voltage division

circuit

Phase

OV detection

voltage

GA

detection

(5V)

f - theta detection

Isolation AMP

Opt

coupler

Opt

Opt coupler

Opt

Opt

High speed

Opt

Opt

Opt

coupler

coupler

coupler

opt coupler

coupler

coupler

coupler

(U-V)

(W-U)

BRD

IUF

IWF

GARXD

TRES

GARES

GASCK

GASRS

TRIP

PHF

US

VS

WS

GS

VDC

MVF1

MVF2

THF

THP

THCOM

PV12

PV12

L

L

NV12

NV12

FFLT

PV5

PV5

PV5

PV5

L

L

L

PV24

PV24

CM1

CM1

IPL

Main board

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(L)

(CM1)

(CM1)

(CM1)

(CM1)

(L)

apprx. 6.4 V at

40 signals between Main

OV level

board and contro l board

Power supply for analog signal

Power supply for digital signal

Power supply for I/F

"H" when

+-3.3Vpeak at

"L" when

"L" when

for communication.

PWM signal

"L" when

Signals for freq.

Temp.

Temp.

BRD is ON

rated output

tripping

phase loss

Operates during

gate

matching

detection on

detection on

"H" when

stopping.

suppress

heatsink

PCB

inst. power

failure

Control board

BRD

VDC

IUF

IWF

TRIP

PHF

GARXD

TRES

GARES GASCK GASRS

US

VS

WS

GS

MVF1

MVF2

THF

THP

L

PV12

PV12

L

L

NV12

NV12

FFLT

PV5

PV5

PV5

PV5

L

L

L

PV24

PV24

CM1

CM1

IPL

AVR

Overcurrent

detection

Output

SH Microprocessor (3.45V)

shutoff circuit

A/D

D/A

10bit

A/D

12bit

Slide switch S1

Emergency

Stop

P24

CM1

CM1

PLC

FW

8

7

6

5

4

3

2

1

TH

FM

CM2

15

14

13

12

11

AL0

AL1

AL2

H

O

O2

OI

L

AM

AMI

Image 55

Contents SJ700-2 Series NTS204X Table of contents Appendix Investigation of the inverter Specification labelModel name,Manufacturing numberMFGPrecautions for Data Setting Function Mode Extended Function Mode PID FEF FUF AVR Electronic thermal characteristic, 2nd B034 Free-setting V/f frequency To 400. Hz FEF FUF FEF FUF FF FEF FUF Term inal C111 FEF FUF FEF FUF RPM Specification FEF FUF FEF FUF Code display system and key operations Page Corresponding to the function code. Data display *1*2 STR key after changing the data Example of operation in full display mode b037 =Pressing the STR key Inverter trip contents,remedy,advise TroubleshootingCPU GA.COM Adjust OFF Option boards error codesInput mode specified by switch settings Setting of MAC ID DIP switches No to No Error code is output when the relevant program runs Trip conditions monitoring 305 A004/A204/A304 A202/A220/A320 *2 006 Initialization setting Page Monitor Modes Debug ModeFunction Modes Setting procedure Inverter SettingHFF/-HFUF/-HFEF Confirming the completion of initializationVDC Control signalPage Daily inspection CleaningPeriodic inspection Daily and Periodic Inspections Ground Resistance Test with a Megger Method of Checking the Inverter and Converter Circuits Replacing Parts Page Page Inverter Replacement Control board SJ700-055-110LF**2 Circuit Diagram Ground Terminal With Jumper SJ700-150LF**2 185LF**2 Circuit DiagramSJ700-220LF**2 Circuit Diagram SJ700-300LF**2 Circuit Diagram SJ700-370LF**2 Circuit Diagram Driver Board SJ700-450LF**2 Circuit DiagramSJ700-550LF**2 Circuit Diagram SJ700-055-110HF**2 Circuit Diagram SJ700-150HF**2 Circuit Diagram SJ700-185HF**2 220HF**2 Circuit Diagram SJ700-300HF**2 Circuit DiagramSJ700-370HF**2 Circuit Diagram TMC CN1 Page Page Page Page Page Page Page Page Page Page Page