Contents
Advance Information
FIXED-POINT Digital Signal Processor
Device characteristics
Characteristics Description
Description
CPU
Functional block diagram
Timers Data Memory Interrupt Selector
Emif
CPU description
Control
Timers
Bit Data C62x CPU
Registers
LD1
RSV2 RSV1 RSV0
Signal groups description
EMU1 EMU0 RSV4 RSV3
Clock/PLL Ieee Standard 1149.1
CE0
CE3 CE2
CE1
BE3 Hold BE2
XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2
Xrdy Xhold Xholda
FIXED-POINT Digital Signal Processor
TMS320C6202
Signal PIN no TYPE² Description Name GJL GLS Expansion BUS
Emif ± Address
Signal PIN no TYPE² Description Name GJL GLS Emif ± Address
Emif ± Data
Multichannel Buffered Serial Port 0 McBSP0
Timers
Emif ± BUS Arbitration
Multichannel Buffered Serial Port 1 McBSP1
Signal PIN no TYPE² Description Name GJL GLS
Multichannel Buffered Serial Port 2 McBSP2
Reserved for Test
AE8
AD6
AE7
Cvdd
AC4
AB4
AC3
AC5 Cvdd
Ground Pins
VSS
GND
Signal PIN no TYPE² Description Name GJL GLS Ground Pins
AF10
Development support
Development Tool Platform Part Number
Scsi TMDS00510WS
TMS
Device Family
Temperature Range Default 0 C to 90 C
Prefix Device Speed Range
Package Type ²
Documentation support
Advance Information
Power-supply sequencing
Clock PLL
Recommended operating conditions
MIN NOM MAX Unit
Parameter Test Conditions MIN TYP MAX Unit
IOL
Signal transition levels
Parameter Measurement Information
IOH
Timing requirements for Xclkin ²³ see Figure
Input and Output Clocks
Timing requirements for CLKIN² see Figure
Clkmode Unit MIN MAX
Parameter
Switching characteristics for CLKOUT1²³ see Figure
Switching characteristics for CLKOUT2 ³ see Figure
Clkmode =
Switching characteristics for XFCLK²³ see Figure
Xfclk Timings
Asynchronous Memory Timing
AWE
Setup = Strobe = Not ready = Hold =
CEx BE30 EA212 ED310
AOE Are AWE Ardy
SYNCHRONOUS-BURST Memory Timing
Unit MIN MAX
EA212 ED310
CEx BE30
BE1 BE2 BE3 BE4
SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²
Synchronous Dram Timing
Timing requirements for synchronous Dram cycles see Figure
CA1 CA2 CA3
Read CLKOUT2
BE1 BE2 BE3
SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²
Dcab
Actv
SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
Refr CLKOUT2
MRS
SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ²
Hold Holda
HOLD/HOLDA Timing
Timing requirements for HOLD/HOLDA cycles ² see Figure
Emif Bus² DSP Owns Bus
Switching characteristics during reset¶ see Figure
Reset Timing
Timing requirements for reset see Figure
Reset CLKOUT1
FIXED-POINT Digital Signal Processor
External Interrupt Timing
EXTINTx, NMI Intr Flag
INUMx
Parameter MIN MAX Unit
Expansion BUS Synchronous Fifo Timing
MIN MAX Unit
XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §
XA2 XA3XA4
XA1
XOE XRE XWE/XWAIT³
XA3 XA4 XOE XRE XWE/XWAIT ³
Expansion BUS Asynchronous Peripheral Timing
XCEx XBE30/XA52 ² XD310
XOE XRE XWE/XWAIT ³ Xrdy §
XOE XRE XWE/XWAIT ³ XRDY§
Expansion BUS Synchronous Host Port Timing
Xblast §
Xclkin XCS XAS Xcntl
XW/R ² XBE30/XA52 ³
XRDY¶
XBLAST§
Xclkin XCS XAS Xcntl XW/R²
XBE30/XA52³
XBE1 XBE2 XBE3 XBE4
TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5
Xclkin XAS
Xblast ³
Xrdy XWE/XWAIT ¶
XBE30/XA52 § Addr XD310
Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #
XBE30/XA52 ² XR/W ³ XD310 Word
Expansion BUS Asynchronous Host Port Timing
XCS Xcntl
Xrdy
External Device as Asynchronous MasterÐWrite
XBE30/XA52² XR/W ³ XD310 Word
XHOLD/XHOLDA Timing
DSP Owns Bus External Requestor Xhold input
XBus ² C6202
Expansion Bus ArbitrationÐInternal Arbiter Disabled
Xhold output Xholda input XBus ² C6202
Multichannel Buffered Serial Port Timing
Timing requirements for McBSP²³ see Figure
Switching characteristics for McBSP²³ see Figure
Bitn-1
Clks Clkr
FSR int
Clkx
Timing requirements for FSR when Gsync = 1 see Figure
Clks
FSR external CLKR/X no need to resync CLKR/Xneeds resync
Master Slave MIN MAX
Master § Slave MIN MAX
Clkx FSX
Bit Bitn-1
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
MASTER§ Slave MIN MAX
FIXED-POINT Digital Signal Processor
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
Timing requirements for timer inputs ² see Figure
DMAC, TIMER, POWER-DOWN Timing
Switching characteristics for Dmac outputs² see Figure
Switching characteristics for timer outputs² see Figure
Switching characteristics for power-down outputs² see Figure
TwPDH Pulse duration, PD high 10P
Jtag TEST-PORT Timing
Switching characteristics for Jtag test port see Figure
DTCKL-TDOV Delay time, TCK low to TDO valid
Timing requirements for Jtag test port see Figure
Thermal resistance characteristics S-PBGA package
Mechanical Data
80 MAX
18,10 16,80 TYP 17,90
Heat Slug
4188959/B 12/98
Important Notice