Texas Instruments TMS320C6202 specifications Clock PLL, Power-supply sequencing

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

clock PLL

All of the internal 'C6202 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.

To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed.

To configure the 'C6202 PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter, a single clean power supply should power both the 'C6202 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input clock timing requirements.

3.3 V

3 OUT

 

 

 

PLLV

 

'320C6202

 

 

 

 

 

 

 

 

 

Filter

 

 

 

 

 

 

 

 

R1

 

 

PLLF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMI

 

 

 

 

CPU Clock

⎟1

CLKOUT1

 

 

 

 

 

 

1 IN

 

 

 

 

 

⎟2

 

2

 

 

 

 

PLLG

 

 

CLKOUT2

 

10 ∝F

0.1 ∝F

C1

C2

CLKMODE2

CLKMODE1

CLKMODE0

 

 

 

 

 

 

 

 

 

 

GND

(Bypass)

 

 

 

 

 

 

 

 

 

 

 

 

CLKIN

 

 

 

 

0

0

0

± MULT ⋅1

f(CPU Clock) = f(CLKIN)

0

0

1

± MULT ⋅4

f(CPU Clock) = f(CLKIN) ⋅4

All Other Modes

± Reserved

 

NOTES: A. The 'C6202 PLL can generate CPU clock frequencies in the range of 130 MHz to 250 MHz. For frequencies below 130 MHz, the PLL should be configured to operate in bypass mode.

B.For the 'C6202, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CPU clock frequency.

C.For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean 3.3-V supply and the PLLG and PLLF terminals should be tied together.

D.The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

E.EMI filter manufacturer TDK part number ACF451832-153-T

F.CLKMODE2 and CLKMODE1 exist only on the GLS device. There are no equivalent connections on the GJL device.

G.The reserved PLL clock modes (GLS devices only) may or may not be supported on future devices as additional PLL multiply factors. For future flexibility, a board can be designed so that these inputs are configurable (either through jumpers, switches, or 0-Ωresistors).

Figure 6. PLL Block Diagram

Table 3. TMS320C6202 PLL Component Selection Table²

 

CLKIN

CPU CLOCK

CLKOUT2

 

 

 

TYPICAL

 

FREQUENCY

R1

C1

C2

CLKMODE

RANGE

RANGE

LOCK TIME

(CLKOUT1)

(Ω)

(nF)

(pF)

 

(MHz)

(MHz)

(∝s)

 

RANGE (MHz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x4

32.5±62.5

130±250

65±125

60.4

27

560

75

²Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 ∝s, the maximum value may be as long as 250 ∝s.

power-supply sequencing

The 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be powered up first, or at the same time as the I/O buffers supply. This is to ensure that the I/O buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board.

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Contents Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Emif Functional block diagramTimers Data Memory Interrupt Selector CPUCPU description Registers TimersBit Data C62x CPU ControlLD1 Clock/PLL Ieee Standard 1149.1 Signal groups descriptionEMU1 EMU0 RSV4 RSV3 RSV2 RSV1 RSV0BE3 Hold BE2 CE3 CE2CE1 CE0Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressMultichannel Buffered Serial Port 1 McBSP1 TimersEmif ± BUS Arbitration Multichannel Buffered Serial Port 0 McBSP0Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test Cvdd AD6AE7 AE8AC5 Cvdd AB4AC3 AC4Ground Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Package Type ² Temperature Range Default 0 C to 90 CPrefix Device Speed Range Device FamilyDocumentation support Advance Information Clock PLL Power-supply sequencingRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit IOH Signal transition levelsParameter Measurement Information IOLClkmode Unit MIN MAX Input and Output ClocksTiming requirements for CLKIN² see Figure Timing requirements for Xclkin ²³ see FigureClkmode = Switching characteristics for CLKOUT1²³ see FigureSwitching characteristics for CLKOUT2 ³ see Figure ParameterXfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingSetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingSDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE² CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingSDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE² Read CLKOUT2BE1 BE2 BE3 CA1 CA2 CA3SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvSDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² DcabRefr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Emif Bus² DSP Owns Bus HOLD/HOLDA TimingTiming requirements for HOLD/HOLDA cycles ² see Figure Hold HoldaReset CLKOUT1 Reset TimingTiming requirements for reset see Figure Switching characteristics during reset¶ see FigureFIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT § Expansion BUS Synchronous Fifo TimingMIN MAX Unit Parameter MIN MAX UnitXA3 XA4 XOE XRE XWE/XWAIT ³ XA1XOE XRE XWE/XWAIT³ XA2 XA3XA4Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing XRDY¶ Xclkin XCS XAS XcntlXW/R ² XBE30/XA52 ³ Xblast §XBE1 XBE2 XBE3 XBE4 Xclkin XCS XAS Xcntl XW/R²XBE30/XA52³ XBLAST§TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310Xrdy Expansion BUS Asynchronous Host Port TimingXCS Xcntl XBE30/XA52 ² XR/W ³ XD310 WordXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure Clkx Clks ClkrFSR int Bitn-1Timing requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for timer outputs² see Figure DMAC, TIMER, POWER-DOWN TimingSwitching characteristics for Dmac outputs² see Figure Timing requirements for timer inputs ² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureTiming requirements for Jtag test port see Figure Switching characteristics for Jtag test port see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingMechanical Data Thermal resistance characteristics S-PBGA package4188959/B 12/98 18,10 16,80 TYP 17,90Heat Slug 80 MAXImportant Notice

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.
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