Contents
Advance Information
FIXED-POINT Digital Signal Processor
Device characteristics
Characteristics Description
Description
Timers Data Memory Interrupt Selector
Functional block diagram
CPU
Emif
CPU description
Bit Data C62x CPU
Timers
Control
Registers
LD1
EMU1 EMU0 RSV4 RSV3
Signal groups description
RSV2 RSV1 RSV0
Clock/PLL Ieee Standard 1149.1
CE1
CE3 CE2
CE0
BE3 Hold BE2
Xrdy Xhold Xholda
XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2
TMS320C6202
FIXED-POINT Digital Signal Processor
Signal PIN no TYPE² Description Name GJL GLS Expansion BUS
Emif ± Address
Emif ± Data
Signal PIN no TYPE² Description Name GJL GLS Emif ± Address
Emif ± BUS Arbitration
Timers
Multichannel Buffered Serial Port 0 McBSP0
Multichannel Buffered Serial Port 1 McBSP1
Signal PIN no TYPE² Description Name GJL GLS
Multichannel Buffered Serial Port 2 McBSP2
Reserved for Test
AE7
AD6
AE8
Cvdd
AC3
AB4
AC4
AC5 Cvdd
Ground Pins
VSS
GND
Signal PIN no TYPE² Description Name GJL GLS Ground Pins
AF10
Development support
Development Tool Platform Part Number
Scsi TMDS00510WS
TMS
Prefix Device Speed Range
Temperature Range Default 0 C to 90 C
Device Family
Package Type ²
Documentation support
Advance Information
Clock PLL
Power-supply sequencing
Recommended operating conditions
MIN NOM MAX Unit
Parameter Test Conditions MIN TYP MAX Unit
Parameter Measurement Information
Signal transition levels
IOL
IOH
Timing requirements for CLKIN² see Figure
Input and Output Clocks
Timing requirements for Xclkin ²³ see Figure
Clkmode Unit MIN MAX
Switching characteristics for CLKOUT2 ³ see Figure
Switching characteristics for CLKOUT1²³ see Figure
Parameter
Clkmode =
Xfclk Timings
Switching characteristics for XFCLK²³ see Figure
AWE
Asynchronous Memory Timing
Setup = Strobe = Not ready = Hold =
CEx BE30 EA212 ED310
AOE Are AWE Ardy
Unit MIN MAX
SYNCHRONOUS-BURST Memory Timing
BE1 BE2 BE3 BE4
CEx BE30
EA212 ED310
SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²
Timing requirements for synchronous Dram cycles see Figure
Synchronous Dram Timing
BE1 BE2 BE3
Read CLKOUT2
CA1 CA2 CA3
SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²
SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
Actv
Dcab
SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
Refr CLKOUT2
MRS
SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ²
Timing requirements for HOLD/HOLDA cycles ² see Figure
HOLD/HOLDA Timing
Hold Holda
Emif Bus² DSP Owns Bus
Timing requirements for reset see Figure
Reset Timing
Switching characteristics during reset¶ see Figure
Reset CLKOUT1
FIXED-POINT Digital Signal Processor
External Interrupt Timing
EXTINTx, NMI Intr Flag
INUMx
MIN MAX Unit
Expansion BUS Synchronous Fifo Timing
Parameter MIN MAX Unit
XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §
XOE XRE XWE/XWAIT³
XA1
XA2 XA3XA4
XA3 XA4 XOE XRE XWE/XWAIT ³
Expansion BUS Asynchronous Peripheral Timing
XCEx XBE30/XA52 ² XD310
XOE XRE XWE/XWAIT ³ Xrdy §
XOE XRE XWE/XWAIT ³ XRDY§
Expansion BUS Synchronous Host Port Timing
XW/R ² XBE30/XA52 ³
Xclkin XCS XAS Xcntl
Xblast §
XRDY¶
XBE30/XA52³
Xclkin XCS XAS Xcntl XW/R²
XBLAST§
XBE1 XBE2 XBE3 XBE4
TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5
Xclkin XAS
Xblast ³
Xrdy XWE/XWAIT ¶
Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #
XBE30/XA52 § Addr XD310
XCS Xcntl
Expansion BUS Asynchronous Host Port Timing
XBE30/XA52 ² XR/W ³ XD310 Word
Xrdy
XBE30/XA52² XR/W ³ XD310 Word
External Device as Asynchronous MasterÐWrite
XHOLD/XHOLDA Timing
DSP Owns Bus External Requestor Xhold input
XBus ² C6202
Xhold output Xholda input XBus ² C6202
Expansion Bus ArbitrationÐInternal Arbiter Disabled
Timing requirements for McBSP²³ see Figure
Multichannel Buffered Serial Port Timing
Switching characteristics for McBSP²³ see Figure
FSR int
Clks Clkr
Bitn-1
Clkx
Timing requirements for FSR when Gsync = 1 see Figure
Clks
FSR external CLKR/X no need to resync CLKR/Xneeds resync
Master § Slave MIN MAX
Master Slave MIN MAX
Bit Bitn-1
Clkx FSX
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
MASTER§ Slave MIN MAX
FIXED-POINT Digital Signal Processor
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
Switching characteristics for Dmac outputs² see Figure
DMAC, TIMER, POWER-DOWN Timing
Timing requirements for timer inputs ² see Figure
Switching characteristics for timer outputs² see Figure
TwPDH Pulse duration, PD high 10P
Switching characteristics for power-down outputs² see Figure
DTCKL-TDOV Delay time, TCK low to TDO valid
Switching characteristics for Jtag test port see Figure
Jtag TEST-PORT Timing
Timing requirements for Jtag test port see Figure
Mechanical Data
Thermal resistance characteristics S-PBGA package
Heat Slug
18,10 16,80 TYP 17,90
80 MAX
4188959/B 12/98
Important Notice