Texas Instruments TMS320C6202 Signal PIN no TYPE² Description Name GJL GLS Expansion BUS

Page 12

ADVANCE INFORMATION

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

 

 

 

 

 

 

Signal Descriptions (Continued)

 

SIGNAL

PIN NO.

TYPE²

DESCRIPTION

 

NAME

GJL

GLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXPANSION BUS

 

 

 

 

 

 

 

 

XCLKIN

A9

C8

I

Expansion bus synchronous host interface clock input

 

 

 

 

 

 

 

 

XFCLK

B9

A8

O

Expansion bus FIFO interface clock output

 

 

 

 

 

 

 

 

XD31

D15

C13

 

 

 

 

 

 

 

 

 

 

XD30

B16

A13

 

 

 

 

 

 

 

 

 

 

XD29

A17

C14

 

 

 

 

 

 

 

 

 

 

XD28

B17

B14

 

 

 

 

 

 

 

 

 

 

XD27

D16

B15

 

 

 

 

 

 

 

 

 

 

XD26

A18

C15

 

 

 

 

 

 

 

 

 

 

XD25

B18

A15

 

 

 

 

 

 

 

 

 

 

XD24

D17

B16

 

 

 

 

 

 

 

 

 

 

XD23

C18

C16

 

 

 

 

 

 

 

 

 

 

XD22

A20

A17

 

 

 

 

 

 

 

 

 

 

XD21

D18

B17

 

 

 

 

 

 

 

 

 

 

XD20

C19

C17

 

Expansion bus data

 

 

 

 

 

 

 

XD19

A21

B18

 

 

 

• Used for transfer of data, address, and control

 

XD18

D19

A19

 

• Also controls initialization of DSP modes and expansion bus at reset via pullup/pulldown

 

 

 

 

 

 

resistors

 

XD17

C20

C18

 

 

 

± XCE[3:0] memory type

 

 

 

 

 

 

 

XD16

B21

B19

 

 

I/O/Z

± XBLAST polarity

 

XD15

A22

C19

± XW/R polarity

 

 

 

 

 

 

 

 

± Asynchronous or synchronous host operation

 

XD14

D20

B20

 

 

 

± Arbitration mode (internal or external)

 

 

 

 

 

 

 

XD13

B22

A21

 

 

 

± FIFO mode

 

XD12

E25

C21

 

± Little endian/big endian

 

 

 

 

 

 

± Boot mode

 

XD11

F24

D20

 

 

 

 

 

 

 

 

 

 

 

 

XD10

E26

B22

 

 

 

 

 

 

 

 

 

 

XD9

F25

D21

 

 

 

 

 

 

 

 

 

 

XD8

G24

E20

 

 

 

 

 

 

 

 

 

 

XD7

H23

E21

 

 

 

 

 

 

 

 

 

 

XD6

F26

D22

 

 

 

 

 

 

 

 

 

 

XD5

G25

F20

 

 

 

 

 

 

 

 

 

 

XD4

J23

F21

 

 

 

 

 

 

 

 

 

 

XD3

G26

E22

 

 

 

 

 

 

 

 

 

 

XD2

H25

G20

 

 

 

 

 

 

 

 

 

 

XD1

J24

G21

 

 

 

 

 

 

 

 

 

 

XD0

K23

G22

 

 

 

 

 

 

 

 

 

 

 

F2

D2

 

 

 

XCE3

 

 

 

 

 

 

 

 

 

Expansion bus I/O port memory space enables

 

 

 

 

 

 

 

XCE2

E1

B1

 

 

O/Z

• Enabled by bits 28, 29, and 30 of the word address

 

 

 

 

 

 

 

 

 

 

 

XCE1

F3

D3

 

 

• Only one asserted during any I/O port data access

 

 

 

 

 

 

 

 

 

E2

C2

 

 

 

XCE0

 

 

 

² I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

12

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Contents Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Functional block diagram Timers Data Memory Interrupt SelectorCPU EmifCPU description Timers Bit Data C62x CPUControl RegistersLD1 Signal groups description EMU1 EMU0 RSV4 RSV3RSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE3 CE2 CE1CE0 BE3 Hold BE2XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 Xrdy Xhold XholdaFIXED-POINT Digital Signal Processor TMS320C6202Signal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Signal PIN no TYPE² Description Name GJL GLS Emif ± Address Emif ± DataTimers Emif ± BUS ArbitrationMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test AD6 AE7AE8 CvddAB4 AC3AC4 AC5 CvddGround Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Temperature Range Default 0 C to 90 C Prefix Device Speed RangeDevice Family Package Type ²Documentation support Advance Information Power-supply sequencing Clock PLLRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Signal transition levels Parameter Measurement InformationIOL IOHInput and Output Clocks Timing requirements for CLKIN² see FigureTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT1²³ see Figure Switching characteristics for CLKOUT2 ³ see FigureParameter Clkmode =Switching characteristics for XFCLK²³ see Figure Xfclk TimingsAsynchronous Memory Timing AWESetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCEx BE30 BE1 BE2 BE3 BE4EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Synchronous Dram Timing Timing requirements for synchronous Dram cycles see FigureRead CLKOUT2 BE1 BE2 BE3CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²Actv SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Dcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Refr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² HOLD/HOLDA Timing Timing requirements for HOLD/HOLDA cycles ² see FigureHold Holda Emif Bus² DSP Owns BusReset Timing Timing requirements for reset see FigureSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx Expansion BUS Synchronous Fifo Timing MIN MAX UnitParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XA1 XOE XRE XWE/XWAIT³XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing Xclkin XCS XAS Xcntl XW/R ² XBE30/XA52 ³Xblast § XRDY¶Xclkin XCS XAS Xcntl XW/R² XBE30/XA52³XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ XBE30/XA52 § Addr XD310 Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #Expansion BUS Asynchronous Host Port Timing XCS XcntlXBE30/XA52 ² XR/W ³ XD310 Word XrdyExternal Device as Asynchronous MasterÐWrite XBE30/XA52² XR/W ³ XD310 WordXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter Disabled Xhold output Xholda input XBus ² C6202Multichannel Buffered Serial Port Timing Timing requirements for McBSP²³ see FigureSwitching characteristics for McBSP²³ see Figure Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master Slave MIN MAX Master § Slave MIN MAXClkx FSX Bit Bitn-1McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = DMAC, TIMER, POWER-DOWN Timing Switching characteristics for Dmac outputs² see FigureTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureSwitching characteristics for power-down outputs² see Figure TwPDH Pulse duration, PD high 10PSwitching characteristics for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureThermal resistance characteristics S-PBGA package Mechanical Data18,10 16,80 TYP 17,90 Heat Slug80 MAX 4188959/B 12/98Important Notice

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.
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