Texas Instruments TMS320C6202 Prefix Device Speed Range, Device Family, Package Type ²

Page 24

ADVANCE INFORMATION

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

device and development-support tool nomenclature (continued)

TMS 320

C 6202 GJL (A) ±250

PREFIX

DEVICE SPEED RANGE

TMX =

Experimental device

±100 MHz

±150 MHz

TMP =

Prototype device

±167 MHz

TMS =

Qualified device

SMJ =

MIL-STD-883C

±200 MHz

±233 MHz

SM

=

High Rel (non-883C)

±250 MHz

DEVICE FAMILY

±300 MHz

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

320 =

TMS320 family

Blank =

0°C to 90°C, commercial temperature

A

=

±40°C to 105°C, extended temperature

PACKAGE TYPE²

N

=

Plastic DIP

TECHNOLOGY

J

=

Ceramic DIP

C

=

CMOS

JD

=

Ceramic DIP side-brazed

GB

=

Ceramic PGA

E

=

CMOS EPROM

FZ

=

Ceramic CC

F

=

CMOS Flash EEPROM

FN

=

Plastic leaded CC

FD

=

Ceramic leadless CC

PJ

=

100-pin plastic EIAJ QFP

PQ

=

132-pin plastic bumpered QFP

PZ

=

100-pin plastic TQFP

PBK =

128-pin plastic TQFP

PGE =

144-pin plastic TQFP

GFN =

256-pin plastic BGA

GGU =

144-pin plastic BGA

GGP =

352-pin plastic BGA

GJC =

352-pin plastic BGA

GJL

=

352-pin plastic BGA

GLS =

384-pin plastic BGA

DEVICE

'1x DSP:

10

16

14

17

15

'2x DSP:

25

26

'2xx DSP:

203

206

240

204

209

'3x DSP:

30

31

32

'4x DSP:

40

44

'5x DSP:

50

53

51

56

52

57

'54x DSP:

541

545

542

546

543

548

² DIP

=

Dual-In-Line Package

'6x DSP:

PGA

=

Pin Grid Array

6201

6201B

CC

=

Chip Carrier

6202

QFP

=

Quad Flat Package

6203

TQFP = Thin Quad Flat Package

6211

6701

BGA

=

Ball Grid Array

6711

Figure 5. TMS320 Device Nomenclature (Including TMS320C6202)

24	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

Image 24

Contents Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Functional block diagram Timers Data Memory Interrupt SelectorCPU EmifCPU description Timers Bit Data C62x CPUControl RegistersLD1 Signal groups description EMU1 EMU0 RSV4 RSV3RSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE3 CE2 CE1CE0 BE3 Hold BE2XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 Xrdy Xhold XholdaFIXED-POINT Digital Signal Processor TMS320C6202Signal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Signal PIN no TYPE² Description Name GJL GLS Emif ± Address Emif ± DataTimers Emif ± BUS ArbitrationMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test AD6 AE7AE8 CvddAB4 AC3AC4 AC5 CvddGround Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Temperature Range Default 0 C to 90 C Prefix Device Speed RangeDevice Family Package Type ²Documentation support Advance Information Power-supply sequencing Clock PLLRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Signal transition levels Parameter Measurement InformationIOL IOHInput and Output Clocks Timing requirements for CLKIN² see FigureTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT1²³ see Figure Switching characteristics for CLKOUT2 ³ see FigureParameter Clkmode =Switching characteristics for XFCLK²³ see Figure Xfclk TimingsAsynchronous Memory Timing AWESetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCEx BE30 BE1 BE2 BE3 BE4EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Synchronous Dram Timing Timing requirements for synchronous Dram cycles see FigureRead CLKOUT2 BE1 BE2 BE3CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²Actv SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Dcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Refr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² HOLD/HOLDA Timing Timing requirements for HOLD/HOLDA cycles ² see FigureHold Holda Emif Bus² DSP Owns BusReset Timing Timing requirements for reset see FigureSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx Expansion BUS Synchronous Fifo Timing MIN MAX UnitParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XA1 XOE XRE XWE/XWAIT³XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing Xclkin XCS XAS Xcntl XW/R ² XBE30/XA52 ³Xblast § XRDY¶Xclkin XCS XAS Xcntl XW/R² XBE30/XA52³XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ XBE30/XA52 § Addr XD310 Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #Expansion BUS Asynchronous Host Port Timing XCS XcntlXBE30/XA52 ² XR/W ³ XD310 Word XrdyExternal Device as Asynchronous MasterÐWrite XBE30/XA52² XR/W ³ XD310 WordXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter Disabled Xhold output Xholda input XBus ² C6202Multichannel Buffered Serial Port Timing Timing requirements for McBSP²³ see FigureSwitching characteristics for McBSP²³ see Figure Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master Slave MIN MAX Master § Slave MIN MAXClkx FSX Bit Bitn-1McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = DMAC, TIMER, POWER-DOWN Timing Switching characteristics for Dmac outputs² see FigureTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureSwitching characteristics for power-down outputs² see Figure TwPDH Pulse duration, PD high 10PSwitching characteristics for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureThermal resistance characteristics S-PBGA package Mechanical Data18,10 16,80 TYP 17,90 Heat Slug80 MAX 4188959/B 12/98Important Notice