Texas Instruments TMS320C6202 specifications Expansion BUS Synchronous Fifo Timing, MIN MAX Unit

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS FIFO TIMING

timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)

NO.

 

 

MIN

MAX

UNIT

 

 

 

 

 

 

5

tsu(XDV-XFCKH)

Setup time, read XDx valid before XFCLK high

2.5

 

ns

6

th(XFCKH-XDV)

Hold time, read XDx valid after XFCLK high

2

 

ns

switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)

NO.

 

PARAMETER

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

td(XFCKH-XCEV)

Delay time, XFCLK high to

 

 

 

 

 

valid

1.5

5.2

ns

XCEx

2

t

Delay time, XFCLK high to

 

 

 

 

 

 

 

 

1.5

5.2

ns

XBE[3:0]/XA[5:2] valid²

 

d(XFCKH-XAV)

 

 

 

 

 

 

 

 

 

 

 

 

 

3

td(XFCKH-XOEV)

Delay time, XFCLK high to

 

 

 

valid

1.5

5.2

ns

XOE

 

4

td(XFCKH-XREV)

Delay time, XFCLK high to

 

 

 

valid

1.5

5.2

ns

XRE

 

7

t

Delay time, XFCLK high to

 

 

 

 

 

 

 

 

 

1.5

5.2

ns

XWE/XWAIT³ valid

 

d(XFCKH-XWEV)

 

 

 

 

 

 

 

 

 

 

 

 

 

8

td(XFCKH-XDV)

Delay time, XFCLK high to XDx valid

 

5.2

ns

9

td(XFCKH-XDIV)

Delay time, XFCLK high to XDx invalid

1.5

 

ns

²XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. ³ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

XFCLK

 

 

 

 

 

 

1

 

 

 

1

XCE3²

 

 

 

 

 

XBE[3:0]/XA[5:2]³

2

 

 

 

2

XA1

XA2

XA3

 

XA4

 

3

 

 

 

3

XOE

 

 

 

 

 

 

4

 

 

 

4

XRE

 

 

 

 

 

XWE/XWAIT§

 

 

6

 

 

 

 

 

 

 

 

 

5

 

 

 

XD[31:0]

 

D1

D2

D3

D4

² FIFO read (glueless) mode only available in XCE3.

³XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. § XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 26. FIFO Read Timing (Glueless Read Mode)

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Contents Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Timers Data Memory Interrupt Selector Functional block diagramCPU EmifCPU description Bit Data C62x CPU TimersControl RegistersLD1 EMU1 EMU0 RSV4 RSV3 Signal groups descriptionRSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE1 CE3 CE2CE0 BE3 Hold BE2Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressEmif ± BUS Arbitration TimersMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test AE7 AD6AE8 CvddAC3 AB4AC4 AC5 CvddGround Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Prefix Device Speed Range Temperature Range Default 0 C to 90 CDevice Family Package Type ²Documentation support Advance Information Clock PLL Power-supply sequencingRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Parameter Measurement Information Signal transition levelsIOL IOHTiming requirements for CLKIN² see Figure Input and Output ClocksTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT2 ³ see Figure Switching characteristics for CLKOUT1²³ see FigureParameter Clkmode =Xfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingSetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingBE1 BE2 BE3 Read CLKOUT2CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvDcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Refr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Timing requirements for HOLD/HOLDA cycles ² see Figure HOLD/HOLDA TimingHold Holda Emif Bus² DSP Owns BusTiming requirements for reset see Figure Reset TimingSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx MIN MAX Unit Expansion BUS Synchronous Fifo TimingParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XOE XRE XWE/XWAIT³ XA1XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing XW/R ² XBE30/XA52 ³ Xclkin XCS XAS XcntlXblast § XRDY¶XBE30/XA52³ Xclkin XCS XAS Xcntl XW/R²XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310XCS Xcntl Expansion BUS Asynchronous Host Port TimingXBE30/XA52 ² XR/W ³ XD310 Word XrdyXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure FSR int Clks ClkrBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for Dmac outputs² see Figure DMAC, TIMER, POWER-DOWN TimingTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Switching characteristics for Jtag test port see FigureJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Thermal resistance characteristics S-PBGA packageHeat Slug 18,10 16,80 TYP 17,9080 MAX 4188959/B 12/98Important Notice

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.
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