Texas Instruments TMS320C6202 specifications CPU description

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Another key feature of the 'C6200 CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The 'C6200 CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically ªtrueº). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. INFORMATIONADVANCE The 32-bit instructions destined for the individual functional units are ªlinkedº together by ª1º bits in the least
significant bit (LSB) position of the instructions. The instructions that are ªchainedº together for simultaneous execution (up to eight in total) compose an execute packet. A ª0º in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-,half-word, or word-addressable.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the 'C6200 CPU from other VLIW architectures.

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

CPU description

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Contents Advance Information FIXED-POINT Digital Signal Processor Description Device characteristicsCharacteristics Description Timers Data Memory Interrupt Selector Functional block diagramCPU EmifCPU description Bit Data C62x CPU TimersControl RegistersLD1 EMU1 EMU0 RSV4 RSV3 Signal groups descriptionRSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE1 CE3 CE2CE0 BE3 Hold BE2Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressEmif ± BUS Arbitration TimersMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Signal PIN no TYPE² Description Name GJL GLSMultichannel Buffered Serial Port 2 McBSP2 AE7 AD6AE8 CvddAC3 AB4AC4 AC5 CvddGND Ground PinsVSS Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Scsi TMDS00510WS Development supportDevelopment Tool Platform Part Number TMS Prefix Device Speed Range Temperature Range Default 0 C to 90 CDevice Family Package Type ²Documentation support Advance Information Clock PLL Power-supply sequencingParameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Parameter Measurement Information Signal transition levelsIOL IOHTiming requirements for CLKIN² see Figure Input and Output ClocksTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT2 ³ see Figure Switching characteristics for CLKOUT1²³ see FigureParameter Clkmode =Xfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingAOE Are AWE Ardy Setup = Strobe = Not ready = Hold =CEx BE30 EA212 ED310 Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingBE1 BE2 BE3 Read CLKOUT2CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvDcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Refr CLKOUT2MRS Timing requirements for HOLD/HOLDA cycles ² see Figure HOLD/HOLDA TimingHold Holda Emif Bus² DSP Owns BusTiming requirements for reset see Figure Reset TimingSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor INUMx External Interrupt TimingEXTINTx, NMI Intr Flag MIN MAX Unit Expansion BUS Synchronous Fifo TimingParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XOE XRE XWE/XWAIT³ XA1XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XOE XRE XWE/XWAIT ³ XRDY§ XCEx XBE30/XA52 ² XD310XOE XRE XWE/XWAIT ³ Xrdy § Expansion BUS Synchronous Host Port Timing XW/R ² XBE30/XA52 ³ Xclkin XCS XAS XcntlXblast § XRDY¶XBE30/XA52³ Xclkin XCS XAS Xcntl XW/R²XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xrdy XWE/XWAIT ¶ Xclkin XASXblast ³ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310XCS Xcntl Expansion BUS Asynchronous Host Port TimingXBE30/XA52 ² XR/W ³ XD310 Word XrdyXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXBus ² C6202 XHOLD/XHOLDA TimingDSP Owns Bus External Requestor Xhold input Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure FSR int Clks ClkrBitn-1 ClkxFSR external CLKR/X no need to resync CLKR/Xneeds resync Timing requirements for FSR when Gsync = 1 see FigureClks Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for Dmac outputs² see Figure DMAC, TIMER, POWER-DOWN TimingTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Switching characteristics for Jtag test port see FigureJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Thermal resistance characteristics S-PBGA packageHeat Slug 18,10 16,80 TYP 17,9080 MAX 4188959/B 12/98Important Notice

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.
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