Texas Instruments TMS320C6202 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =

Page 68

ADVANCE INFORMATION

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1²³ (see Figure 45)

 

 

 

 

'C6202-200

 

 

 

 

 

 

'C6202-233

 

 

NO.

 

 

 

'C6202-250

 

UNIT

 

 

 

 

 

 

 

 

 

MASTER

SLAVE

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

4

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

12

 

2 ± 3P

 

ns

5

th(CKXL-DRV)

Hold time, DR valid after CLKX low

4

 

5 + 6P

 

ns

² P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1²³ (see Figure 45)

 

 

 

 

'C6202-200

 

 

 

 

 

 

'C6202-233

 

 

NO.

 

PARAMETER

 

'C6202-250

 

UNIT

 

 

 

 

 

 

 

 

MASTER§

SLAVE

 

 

 

 

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

1

t

Hold time, FSX low after CLKX high

H ± 2

H + 3

 

 

ns

 

h(CKXH-FXL)

 

 

 

 

 

 

2

t

Delay time, FSX low to CLKX low#

T ± 2

T + 1

 

 

ns

 

d(FXL-CKXL)

 

 

 

 

 

 

3

td(CKXH-DXV)

Delay time, CLKX high to DX valid

±2

4

3P + 4

5P + 17

ns

6

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

±2

4

3P + 3

5P + 17

ns

CLKX high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

td(FXL-DXV)

Delay time, FSX low to DX valid

L ± 2

L + 4

2P + 2

4P + 17

ns

² P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =

CLKX period = (1 + CLKGDV) * S

H =

CLKX high pulse width

= (CLKGDV/2 + 1) * S if CLKGDV is even

 

 

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

=(CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

CLKX

 

 

 

 

 

 

1

2

 

 

 

FSX

 

 

 

 

 

 

6

7

3

 

 

DX

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

 

 

4

5

 

 

 

 

 

 

 

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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Contents Advance Information FIXED-POINT Digital Signal Processor Description Device characteristicsCharacteristics Description Functional block diagram Timers Data Memory Interrupt SelectorCPU EmifCPU description Timers Bit Data C62x CPUControl RegistersLD1 Signal groups description EMU1 EMU0 RSV4 RSV3RSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE3 CE2 CE1CE0 BE3 Hold BE2XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 Xrdy Xhold XholdaFIXED-POINT Digital Signal Processor TMS320C6202Signal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Signal PIN no TYPE² Description Name GJL GLS Emif ± Address Emif ± DataTimers Emif ± BUS ArbitrationMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Signal PIN no TYPE² Description Name GJL GLSMultichannel Buffered Serial Port 2 McBSP2 AD6 AE7AE8 CvddAB4 AC3AC4 AC5 CvddGND Ground PinsVSS Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Scsi TMDS00510WS Development supportDevelopment Tool Platform Part Number TMS Temperature Range Default 0 C to 90 C Prefix Device Speed RangeDevice Family Package Type ²Documentation support Advance Information Power-supply sequencing Clock PLLParameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Signal transition levels Parameter Measurement InformationIOL IOHInput and Output Clocks Timing requirements for CLKIN² see FigureTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT1²³ see Figure Switching characteristics for CLKOUT2 ³ see FigureParameter Clkmode =Switching characteristics for XFCLK²³ see Figure Xfclk TimingsAsynchronous Memory Timing AWEAOE Are AWE Ardy Setup = Strobe = Not ready = Hold =CEx BE30 EA212 ED310 SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCEx BE30 BE1 BE2 BE3 BE4EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Synchronous Dram Timing Timing requirements for synchronous Dram cycles see FigureRead CLKOUT2 BE1 BE2 BE3CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²Actv SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Dcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Refr CLKOUT2MRS HOLD/HOLDA Timing Timing requirements for HOLD/HOLDA cycles ² see FigureHold Holda Emif Bus² DSP Owns BusReset Timing Timing requirements for reset see FigureSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor INUMx External Interrupt TimingEXTINTx, NMI Intr Flag Expansion BUS Synchronous Fifo Timing MIN MAX UnitParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XA1 XOE XRE XWE/XWAIT³XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XOE XRE XWE/XWAIT ³ XRDY§ XCEx XBE30/XA52 ² XD310XOE XRE XWE/XWAIT ³ Xrdy § Expansion BUS Synchronous Host Port Timing Xclkin XCS XAS Xcntl XW/R ² XBE30/XA52 ³Xblast § XRDY¶Xclkin XCS XAS Xcntl XW/R² XBE30/XA52³XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xrdy XWE/XWAIT ¶ Xclkin XASXblast ³ XBE30/XA52 § Addr XD310 Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #Expansion BUS Asynchronous Host Port Timing XCS XcntlXBE30/XA52 ² XR/W ³ XD310 Word XrdyExternal Device as Asynchronous MasterÐWrite XBE30/XA52² XR/W ³ XD310 WordXBus ² C6202 XHOLD/XHOLDA TimingDSP Owns Bus External Requestor Xhold input Expansion Bus ArbitrationÐInternal Arbiter Disabled Xhold output Xholda input XBus ² C6202Multichannel Buffered Serial Port Timing Timing requirements for McBSP²³ see FigureSwitching characteristics for McBSP²³ see Figure Clks Clkr FSR intBitn-1 ClkxFSR external CLKR/X no need to resync CLKR/Xneeds resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAX Master § Slave MIN MAXClkx FSX Bit Bitn-1McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = DMAC, TIMER, POWER-DOWN Timing Switching characteristics for Dmac outputs² see FigureTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureSwitching characteristics for power-down outputs² see Figure TwPDH Pulse duration, PD high 10PSwitching characteristics for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureThermal resistance characteristics S-PBGA package Mechanical Data18,10 16,80 TYP 17,90 Heat Slug80 MAX 4188959/B 12/98Important Notice

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.
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