Contents
Advance Information
FIXED-POINT Digital Signal Processor
Device characteristics
Characteristics Description
Description
Emif
Functional block diagram
Timers Data Memory Interrupt Selector
CPU
CPU description
Registers
Timers
Bit Data C62x CPU
Control
LD1
Clock/PLL Ieee Standard 1149.1
Signal groups description
EMU1 EMU0 RSV4 RSV3
RSV2 RSV1 RSV0
BE3 Hold BE2
CE3 CE2
CE1
CE0
Xrdy Xhold Xholda
XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2
TMS320C6202
FIXED-POINT Digital Signal Processor
Signal PIN no TYPE² Description Name GJL GLS Expansion BUS
Emif ± Address
Emif ± Data
Signal PIN no TYPE² Description Name GJL GLS Emif ± Address
Multichannel Buffered Serial Port 1 McBSP1
Timers
Emif ± BUS Arbitration
Multichannel Buffered Serial Port 0 McBSP0
Signal PIN no TYPE² Description Name GJL GLS
Multichannel Buffered Serial Port 2 McBSP2
Reserved for Test
Cvdd
AD6
AE7
AE8
AC5 Cvdd
AB4
AC3
AC4
Ground Pins
VSS
GND
Signal PIN no TYPE² Description Name GJL GLS Ground Pins
AF10
Development support
Development Tool Platform Part Number
Scsi TMDS00510WS
TMS
Package Type ²
Temperature Range Default 0 C to 90 C
Prefix Device Speed Range
Device Family
Documentation support
Advance Information
Clock PLL
Power-supply sequencing
Recommended operating conditions
MIN NOM MAX Unit
Parameter Test Conditions MIN TYP MAX Unit
IOH
Signal transition levels
Parameter Measurement Information
IOL
Clkmode Unit MIN MAX
Input and Output Clocks
Timing requirements for CLKIN² see Figure
Timing requirements for Xclkin ²³ see Figure
Clkmode =
Switching characteristics for CLKOUT1²³ see Figure
Switching characteristics for CLKOUT2 ³ see Figure
Parameter
Xfclk Timings
Switching characteristics for XFCLK²³ see Figure
AWE
Asynchronous Memory Timing
Setup = Strobe = Not ready = Hold =
CEx BE30 EA212 ED310
AOE Are AWE Ardy
Unit MIN MAX
SYNCHRONOUS-BURST Memory Timing
SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²
CEx BE30
BE1 BE2 BE3 BE4
EA212 ED310
Timing requirements for synchronous Dram cycles see Figure
Synchronous Dram Timing
SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²
Read CLKOUT2
BE1 BE2 BE3
CA1 CA2 CA3
SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
Actv
SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
Dcab
Refr CLKOUT2
MRS
SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ²
Emif Bus² DSP Owns Bus
HOLD/HOLDA Timing
Timing requirements for HOLD/HOLDA cycles ² see Figure
Hold Holda
Reset CLKOUT1
Reset Timing
Timing requirements for reset see Figure
Switching characteristics during reset¶ see Figure
FIXED-POINT Digital Signal Processor
External Interrupt Timing
EXTINTx, NMI Intr Flag
INUMx
XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §
Expansion BUS Synchronous Fifo Timing
MIN MAX Unit
Parameter MIN MAX Unit
XA3 XA4 XOE XRE XWE/XWAIT ³
XA1
XOE XRE XWE/XWAIT³
XA2 XA3XA4
Expansion BUS Asynchronous Peripheral Timing
XCEx XBE30/XA52 ² XD310
XOE XRE XWE/XWAIT ³ Xrdy §
XOE XRE XWE/XWAIT ³ XRDY§
Expansion BUS Synchronous Host Port Timing
XRDY¶
Xclkin XCS XAS Xcntl
XW/R ² XBE30/XA52 ³
Xblast §
XBE1 XBE2 XBE3 XBE4
Xclkin XCS XAS Xcntl XW/R²
XBE30/XA52³
XBLAST§
TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5
Xclkin XAS
Xblast ³
Xrdy XWE/XWAIT ¶
Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #
XBE30/XA52 § Addr XD310
Xrdy
Expansion BUS Asynchronous Host Port Timing
XCS Xcntl
XBE30/XA52 ² XR/W ³ XD310 Word
XBE30/XA52² XR/W ³ XD310 Word
External Device as Asynchronous MasterÐWrite
XHOLD/XHOLDA Timing
DSP Owns Bus External Requestor Xhold input
XBus ² C6202
Xhold output Xholda input XBus ² C6202
Expansion Bus ArbitrationÐInternal Arbiter Disabled
Timing requirements for McBSP²³ see Figure
Multichannel Buffered Serial Port Timing
Switching characteristics for McBSP²³ see Figure
Clkx
Clks Clkr
FSR int
Bitn-1
Timing requirements for FSR when Gsync = 1 see Figure
Clks
FSR external CLKR/X no need to resync CLKR/Xneeds resync
Master § Slave MIN MAX
Master Slave MIN MAX
Bit Bitn-1
Clkx FSX
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
MASTER§ Slave MIN MAX
FIXED-POINT Digital Signal Processor
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
Switching characteristics for timer outputs² see Figure
DMAC, TIMER, POWER-DOWN Timing
Switching characteristics for Dmac outputs² see Figure
Timing requirements for timer inputs ² see Figure
TwPDH Pulse duration, PD high 10P
Switching characteristics for power-down outputs² see Figure
Timing requirements for Jtag test port see Figure
Switching characteristics for Jtag test port see Figure
DTCKL-TDOV Delay time, TCK low to TDO valid
Jtag TEST-PORT Timing
Mechanical Data
Thermal resistance characteristics S-PBGA package
4188959/B 12/98
18,10 16,80 TYP 17,90
Heat Slug
80 MAX
Important Notice