Contents
Advance Information
FIXED-POINT Digital Signal Processor
Description
Device characteristics
Characteristics Description
Functional block diagram
Timers Data Memory Interrupt Selector
CPU
Emif
CPU description
Timers
Bit Data C62x CPU
Control
Registers
LD1
Signal groups description
EMU1 EMU0 RSV4 RSV3
RSV2 RSV1 RSV0
Clock/PLL Ieee Standard 1149.1
CE3 CE2
CE1
CE0
BE3 Hold BE2
XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2
Xrdy Xhold Xholda
FIXED-POINT Digital Signal Processor
TMS320C6202
Signal PIN no TYPE² Description Name GJL GLS Expansion BUS
Emif ± Address
Signal PIN no TYPE² Description Name GJL GLS Emif ± Address
Emif ± Data
Timers
Emif ± BUS Arbitration
Multichannel Buffered Serial Port 0 McBSP0
Multichannel Buffered Serial Port 1 McBSP1
Reserved for Test
Signal PIN no TYPE² Description Name GJL GLS
Multichannel Buffered Serial Port 2 McBSP2
AD6
AE7
AE8
Cvdd
AB4
AC3
AC4
AC5 Cvdd
GND
Ground Pins
VSS
Signal PIN no TYPE² Description Name GJL GLS Ground Pins
AF10
Scsi TMDS00510WS
Development support
Development Tool Platform Part Number
TMS
Temperature Range Default 0 C to 90 C
Prefix Device Speed Range
Device Family
Package Type ²
Documentation support
Advance Information
Power-supply sequencing
Clock PLL
Parameter Test Conditions MIN TYP MAX Unit
Recommended operating conditions
MIN NOM MAX Unit
Signal transition levels
Parameter Measurement Information
IOL
IOH
Input and Output Clocks
Timing requirements for CLKIN² see Figure
Timing requirements for Xclkin ²³ see Figure
Clkmode Unit MIN MAX
Switching characteristics for CLKOUT1²³ see Figure
Switching characteristics for CLKOUT2 ³ see Figure
Parameter
Clkmode =
Switching characteristics for XFCLK²³ see Figure
Xfclk Timings
Asynchronous Memory Timing
AWE
AOE Are AWE Ardy
Setup = Strobe = Not ready = Hold =
CEx BE30 EA212 ED310
SYNCHRONOUS-BURST Memory Timing
Unit MIN MAX
CEx BE30
BE1 BE2 BE3 BE4
EA212 ED310
SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²
Synchronous Dram Timing
Timing requirements for synchronous Dram cycles see Figure
Read CLKOUT2
BE1 BE2 BE3
CA1 CA2 CA3
SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²
Actv
SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
Dcab
SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²
SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ²
Refr CLKOUT2
MRS
HOLD/HOLDA Timing
Timing requirements for HOLD/HOLDA cycles ² see Figure
Hold Holda
Emif Bus² DSP Owns Bus
Reset Timing
Timing requirements for reset see Figure
Switching characteristics during reset¶ see Figure
Reset CLKOUT1
FIXED-POINT Digital Signal Processor
INUMx
External Interrupt Timing
EXTINTx, NMI Intr Flag
Expansion BUS Synchronous Fifo Timing
MIN MAX Unit
Parameter MIN MAX Unit
XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §
XA1
XOE XRE XWE/XWAIT³
XA2 XA3XA4
XA3 XA4 XOE XRE XWE/XWAIT ³
Expansion BUS Asynchronous Peripheral Timing
XOE XRE XWE/XWAIT ³ XRDY§
XCEx XBE30/XA52 ² XD310
XOE XRE XWE/XWAIT ³ Xrdy §
Expansion BUS Synchronous Host Port Timing
Xclkin XCS XAS Xcntl
XW/R ² XBE30/XA52 ³
Xblast §
XRDY¶
Xclkin XCS XAS Xcntl XW/R²
XBE30/XA52³
XBLAST§
XBE1 XBE2 XBE3 XBE4
TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5
Xrdy XWE/XWAIT ¶
Xclkin XAS
Xblast ³
XBE30/XA52 § Addr XD310
Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #
Expansion BUS Asynchronous Host Port Timing
XCS Xcntl
XBE30/XA52 ² XR/W ³ XD310 Word
Xrdy
External Device as Asynchronous MasterÐWrite
XBE30/XA52² XR/W ³ XD310 Word
XBus ² C6202
XHOLD/XHOLDA Timing
DSP Owns Bus External Requestor Xhold input
Expansion Bus ArbitrationÐInternal Arbiter Disabled
Xhold output Xholda input XBus ² C6202
Multichannel Buffered Serial Port Timing
Timing requirements for McBSP²³ see Figure
Switching characteristics for McBSP²³ see Figure
Clks Clkr
FSR int
Bitn-1
Clkx
FSR external CLKR/X no need to resync CLKR/Xneeds resync
Timing requirements for FSR when Gsync = 1 see Figure
Clks
Master Slave MIN MAX
Master § Slave MIN MAX
Clkx FSX
Bit Bitn-1
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
MASTER§ Slave MIN MAX
FIXED-POINT Digital Signal Processor
McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =
DMAC, TIMER, POWER-DOWN Timing
Switching characteristics for Dmac outputs² see Figure
Timing requirements for timer inputs ² see Figure
Switching characteristics for timer outputs² see Figure
Switching characteristics for power-down outputs² see Figure
TwPDH Pulse duration, PD high 10P
Switching characteristics for Jtag test port see Figure
DTCKL-TDOV Delay time, TCK low to TDO valid
Jtag TEST-PORT Timing
Timing requirements for Jtag test port see Figure
Thermal resistance characteristics S-PBGA package
Mechanical Data
18,10 16,80 TYP 17,90
Heat Slug
80 MAX
4188959/B 12/98
Important Notice