Texas Instruments TMS320C6202 Expansion BUS Asynchronous Peripheral Timing, C6202-200 C6202-233

Page 47

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING

timing requirements for asynchronous peripheral cycles² (see Figure 29±Figure 30)

			'C6202-200
NO.			'C6202-233		UNIT
NO.			'C6202-250		UNIT
			'C6202-250

			MIN	MAX

4	tsu(XDV-CKO1H)	Setup time, read XDx valid before CLKOUT1 high	4.0		ns
5	th(CKO1H-XDV)	Hold time, read XDx valid after CLKOUT1 high	0		ns
8	tsu(XRY-CKO1H)	Setup time, XRDY valid before CLKOUT1 high	4.0		ns
9	th(CKO1H-XRY)	Hold time, XRDY valid after CLKOUT1 high	0		ns

²To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.

switching characteristics for asynchronous peripheral cycles³§¶ (see Figure 29±Figure 30)

'C6202-200

NO.

PARAMETER

'C6202-233

UNIT

'C6202-250

MIN

MAX

1

td(CKO1H-XCEV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

XCEx

2

td(CKO1H-XAV)

Delay time, CLKOUT1 high to

0

4.0

ns

XBE[3:0]/XA[5:2] valid

3

td(CKO1H-XAIV)

Delay time, CLKOUT1 high to

0

4.0

ns

XBE[3:0]/XA[5:2] invalid

6

td(CKO1H-XOEV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

XOE

7

td(CKO1H-XREV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

XRE

10

td(CKO1H-XDV)

Delay time, CLKOUT1 high to XDx valid

4.0

ns

11

td(CKO1H-XDIV)

Delay time, CLKOUT1 high to XDx invalid

0

ns

12

td(CKO1H-XWEV)

Delay time, CLKOUT1 high to

0

4.0

ns

XWE/XWAIT valid

³ The minimum delay is also the minimum output hold after CLKOUT1 high.

§XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses. ¶ XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

47

Image 47

Contents Advance Information FIXED-POINT Digital Signal Processor Description Device characteristicsCharacteristics Description Emif Functional block diagramTimers Data Memory Interrupt Selector CPUCPU description Registers TimersBit Data C62x CPU ControlLD1 Clock/PLL Ieee Standard 1149.1 Signal groups descriptionEMU1 EMU0 RSV4 RSV3 RSV2 RSV1 RSV0BE3 Hold BE2 CE3 CE2CE1 CE0Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressMultichannel Buffered Serial Port 1 McBSP1 TimersEmif ± BUS Arbitration Multichannel Buffered Serial Port 0 McBSP0Reserved for Test Signal PIN no TYPE² Description Name GJL GLSMultichannel Buffered Serial Port 2 McBSP2 Cvdd AD6AE7 AE8AC5 Cvdd AB4AC3 AC4GND Ground PinsVSS Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Scsi TMDS00510WS Development supportDevelopment Tool Platform Part Number TMS Package Type ² Temperature Range Default 0 C to 90 CPrefix Device Speed Range Device FamilyDocumentation support Advance Information Clock PLL Power-supply sequencingParameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit IOH Signal transition levelsParameter Measurement Information IOLClkmode Unit MIN MAX Input and Output ClocksTiming requirements for CLKIN² see Figure Timing requirements for Xclkin ²³ see FigureClkmode = Switching characteristics for CLKOUT1²³ see FigureSwitching characteristics for CLKOUT2 ³ see Figure ParameterXfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingAOE Are AWE Ardy Setup = Strobe = Not ready = Hold =CEx BE30 EA212 ED310 Unit MIN MAX SYNCHRONOUS-BURST Memory TimingSDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE² CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingSDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE² Read CLKOUT2BE1 BE2 BE3 CA1 CA2 CA3SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvSDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² DcabSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Refr CLKOUT2MRS Emif Bus² DSP Owns Bus HOLD/HOLDA TimingTiming requirements for HOLD/HOLDA cycles ² see Figure Hold HoldaReset CLKOUT1 Reset TimingTiming requirements for reset see Figure Switching characteristics during reset¶ see FigureFIXED-POINT Digital Signal Processor INUMx External Interrupt Timing EXTINTx, NMI Intr Flag XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT § Expansion BUS Synchronous Fifo TimingMIN MAX Unit Parameter MIN MAX UnitXA3 XA4 XOE XRE XWE/XWAIT ³ XA1XOE XRE XWE/XWAIT³ XA2 XA3XA4Expansion BUS Asynchronous Peripheral Timing XOE XRE XWE/XWAIT ³ XRDY§ XCEx XBE30/XA52 ² XD310XOE XRE XWE/XWAIT ³ Xrdy § Expansion BUS Synchronous Host Port Timing XRDY¶ Xclkin XCS XAS XcntlXW/R ² XBE30/XA52 ³ Xblast §XBE1 XBE2 XBE3 XBE4 Xclkin XCS XAS Xcntl XW/R²XBE30/XA52³ XBLAST§TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xrdy XWE/XWAIT ¶ Xclkin XASXblast ³ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310Xrdy Expansion BUS Asynchronous Host Port TimingXCS Xcntl XBE30/XA52 ² XR/W ³ XD310 WordXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXBus ² C6202 XHOLD/XHOLDA TimingDSP Owns Bus External Requestor Xhold input Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure Clkx Clks ClkrFSR int Bitn-1FSR external CLKR/X no need to resync CLKR/Xneeds resync Timing requirements for FSR when Gsync = 1 see FigureClks Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for timer outputs² see Figure DMAC, TIMER, POWER-DOWN TimingSwitching characteristics for Dmac outputs² see Figure Timing requirements for timer inputs ² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureTiming requirements for Jtag test port see Figure Switching characteristics for Jtag test port see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingMechanical Data Thermal resistance characteristics S-PBGA package4188959/B 12/98 18,10 16,80 TYP 17,90Heat Slug 80 MAXImportant Notice