Cypress CYDC256B16 manuals
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Cypress CYDC256B16 Manual
26 pages 602.07 Kb
1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAMCYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,Features Selection Guide for VCC = 1.8V Selection Guide for VCC = 2.5V Selection Guide for VCC = 3.0V 2 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,Document #: 001-01638 Rev. *E Page 2 of 26 Figure 1. Top Level Block Diagram Document #: 001-01638 Rev. *E Page 3 of 26 Pin Configurations 3 CYDC064B16 CYDC128B16 CYDC256B164 CYDC064B16, CYDC128B08, CYDC064B08CYDC128B08 CYDC064B08 5 CYDC256B16, CYDC128B16,Functional Description Pin Definitions 6 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B088 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B0812 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,16 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,Switching Characteristics for VCC = 3.0V Over the Operating Range Switching Characteristics for VCC = 2.5V Over the Operating Range (continued) 17 Switching Characteristics for VCC = 3.0V Over the Operating Range (continued)18 Switching WaveformsRead Cycle No.1 (Either Port Address Access) Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40] Read Cycle No. 3 (Either Port) 19 Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46]Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48] 20 Semaphore Read After Write Timing, Either SideTiming Diagram of Semaphore Contention 21 Timing Diagram of Read with BUSY (M/S=HIGH)[53]Write Timing with Busy Input (M/S = LOW) 22 Busy Timing Diagram No.1 (CE Arbitration)CER Valid First Right Address Valid First Busy Timing Diagram No.2 (Address Arbitration) CEL Valid First[54] 23 Interrupt Timing Diagrams Right Side Sets INTL: Right Side Clears INTR: Left Side Sets INTR: Left Side Clears INTL: 24 Ordering Information 26 Document History Page
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