CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E Page 19 of 26
Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46]Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48]Notes:
43.tHA is measured from the earlier of CE or R/W or (SEM or R/W ) going HIGH at the end of write cycle.
44.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tPWE.
45.To access RAM, CE = VIL, SEM = VIH.
46.To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
47.Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
48.During this period, the I/O pins are in the output state, and input signals must not be applied.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
[47]
[47]
[44]
[45, 46]
NOTE 48 NOTE 48
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
[45, 46]
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