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Cypress CYDC128B08 manual Switching Waveforms, Read Cycle No.1 Either Port Address Access36, 37

Models: CYDC256B16 CYDC128B16 CYDC128B08 CYDC064B08 CYDC064B16

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Waveforms

Read Cycle No.1 (Either Port Address Access)[36, 37, 38]

		tRC
ADDRESS
	tAA	tOHA
	tOHA	tOHA
DATA OUT	PREVIOUS DATA VALID	DATA VALID

Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40]

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT

ISB

	tACE
	tHZCE
	tDOE
	tHZOE
	tLZOE
	DATA VALID
	tLZCE
tPU	t
	PD

Read Cycle No. 3 (Either Port)[36, 38, 41, 42]

tRC

ADDRESS

tAA

UB or LB

tLZCE

tABE

CE

tACE

tLZCE

DATA OUT

tOHA

tHZCE

tHZCE

Notes:

36.R/W is HIGH for read cycles.

37.Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

38.OE = VIL.

39.Address valid prior to or coincident with CE transition LOW.

40.To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

41.R/W must be HIGH during all address transitions.

42.A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

Document #: 001-01638 Rev. *E

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Cypress CYDC128B08, CYDC064B16, CYDC064B08, CYDC256B16 Switching Waveforms, Read Cycle No.1 Either Port Address Access36, 37

Contents

CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 FeaturesSelection Guide for VCC = Unit CYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top View Pin Configurations 7, 8, 9 CYDC064B08 Pin Definitions Functional Description Master/Slave InterruptsBusy Input Read Register Architecture Input Read Register Operation16 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Semaphore Operation Example Function Maximum Ratings23 Electrical Characteristics for V CC =Range Ambient Temperature Operating Range Input Leakage Current Standb y Cur rent One Port Cmos Ind Input High Voltage 5V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input LOW Voltage 5V any port 0V any port Capacitance Parameter Description Test Conditions Max Unit AC7Test Loads and Waveforms Write Cycle Busy Timing Interrupt TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.2 Either Port CE/OE Access36, 39 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No Either Port36, 38, 41 Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOW Busy Timing Diagram No.1 CE Arbitration CEL Valid First54 CER Valid FirstRight Address Valid First Right Side Sets Intl Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Left Side Clears INT L Ordering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100 Issue Date Orig. Description of Change Document History