Cypress CYDC064B08, CYDC064B16, CYDC128B08, CYDC128B16, CYDC256B16 Semaphore Read After Write Timing, Either Side, Timing Diagram of Semaphore Contention

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Document #: 001-01638 Rev. *E Page 20 of 26

Semaphore Read After Write Timing, Either Side[49, 50]

Timing Diagram of Semaphore Contention[51, 52]

Notes:

49.If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

50.CE = HIGH for the duration of the above timing (both write and read cycle).

51.I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

52.If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.

Switching Waveforms (continued)

tSOP

tSAA

VALID ADRESS VALID ADRESS

tHD

DATAIN VALID

tOHA

tAW

tHA

tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

R/W

I/O0

SEM

A0–A2

DATAOUT VALID

MATCH

tSPS

MATCH

R/WL

SEML

R/WR

SEMR

A0L–A2L

A0R–A2R

[+] Feedback

Contents

Main 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Features Selection Guide for VCC = 1.8V Selection Guide for VCC = 2.5V CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Document #: 001-01638 Rev. *E Page 2 of 26 Figure 1. Top Level Block Diagram Document #: 001-01638 Rev. *E Page 3 of 26 Pin Configurations CYDC064B16 CYDC128B16 CYDC256B16 CYDC064B16, CYDC128B08, CYDC064B08 Pin Configurations CYDC128B08 CYDC064B08 100-pin TQFP (Top View) CYDC256B16, CYDC128B16, Functional Description Pin Definitions CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Architecture CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Maximum Ratings Operating Range Electrical Characteristics for VCC = 1.8V Over the Operating Range Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range Electrical Characteristics for VCC = 2.5V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Electrical Characteristics for 3.0V Capacitance AC Test Loads and Waveforms Switching Characteristics for VCC = 1.8V Over the Operating Range[27] Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued) Switching Characteristics for VCC = 2.5V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Switching Characteristics for VCC = 3.0V Over the Operating Range Switching Characteristics for VCC = 2.5V Over the Operating Range (continued) Switching Characteristics for VCC = 3.0V Over the Operating Range (continued) Switching Waveforms Read Cycle No.1 (Either Port Address Access) Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40] Read Cycle No. 3 (Either Port) Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46] Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48] Semaphore Read After Write Timing, Either Side Timing Diagram of Semaphore Contention Timing Diagram of Read with BUSY (M/S=HIGH)[53] Write Timing with Busy Input (M/S = LOW) Busy Timing Diagram No.1 (CE Arbitration) CER Valid First Right Address Valid First Busy Timing Diagram No.2 (Address Arbitration) CEL Valid First[54] Interrupt Timing Diagrams Right Side Sets INTL: Right Side Clears INTR: Left Side Sets INTR: Ordering Information Page Document History Page

Cypress Semaphore Read After Write Timing, Either Side, Timing Diagram of Semaphore Contention

Models: CYDC064B08 CYDC064B16 CYDC128B08 CYDC128B16 CYDC256B16