CYDC256B16, CYDC128B16 | Cypress CYDC064B16, CYDC064B08 specification

				CYDC256B16, CYDC128B16,
				CYDC064B16, CYDC128B08,
					CYDC064B08
I/O[15:0]L					I/O[15:0]R
I/O[15:0]L					UBR
UBL					UBR
LBL		IO		IO	LBR
		Control		Control
			16K X 16
		Dual Ported Array
		Address Decode		Address Decode
A[13:0]L					A [13:0]R
CE L			Interrupt		CE R
OE L			Interrupt		OE R
OE L			Arbitration		OE R
R/W L			Semaphore		R/W R
SEM	L				SEMR
	L				BUSY R
BUSY L					BUSY R
	INTL	Mailboxes	INT	M/S
	INTL	Mailboxes	INT	R
				R
			Input Read
		CEL	Register and		CE R
		OEL	Output Drive		OE R
		OEL	Register		OE R
		R/WL	Register		R/W R
IRR0 ,IRR1		R/WL			R/W R
IRR0 ,IRR1				ODR0 - ODR4
				ODR0 - ODR4
				SFEN

Figure 1. Top Level Block Diagram[1, 2]

Notes:

1.A0–A11for 4k devices; A0–A12for 8k devices; A0–A13for 16k devices.

2.BUSY is an output in master mode and an input in slave mode.

Document #: 001-01638 Rev. *E

Page 2 of 26

[+] Feedback

Image 2

Cypress CYDC064B16, CYDC064B08, CYDC128B08 manual CYDC256B16, CYDC128B16

Contents

CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 FeaturesSelection Guide for VCC = Unit CYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top View Pin Configurations 7, 8, 9 CYDC064B08 Pin Definitions Functional Description Master/Slave InterruptsBusy Input Read Register Architecture Input Read Register Operation16 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Semaphore Operation Example Function Maximum Ratings23 Electrical Characteristics for V CC =Range Ambient Temperature Operating Range Input Leakage Current Standb y Cur rent One Port Cmos Ind Input High Voltage 5V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input LOW Voltage 5V any port 0V any port Capacitance Parameter Description Test Conditions Max Unit AC7Test Loads and Waveforms Write Cycle Semaphore Timing Busy TimingInterrupt Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.2 Either Port CE/OE Access36, 39 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No Either Port36, 38, 41 Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOW Right Address Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54CER Valid First Right Side Sets Intl Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Left Side Clears INT L Ordering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100 Issue Date Orig. Description of Change Document History