CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E Page 13 of 26
7
AC Test Loads and WaveformsSwitching Characteristics for VCC = 1.8V Over the Operating Range[27]
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 40 55 ns
tAA Address to Data Valid 40 55 ns
tOHA Output Hold From Address Change 5 5 ns
tACE[28] CE LOW to Data Valid 40 55 ns
tDOE OE LOW to Data Valid 25 30 ns
tLZOE[29, 30, 31] OE Low to Low Z 5 5 ns
tHZOE[29, 30, 31] OE HIGH to High Z 15 25 ns
tLZCE[29, 30, 31] CE LOW to Low Z 5 5 ns
tHZCE[29, 30, 31] CE HIGH to High Z 15 25 ns
tPU[31] CE LOW to Power-Up 0 0 ns
tPD[31] CE HIGH to Power-Down 40 55 ns
tABE[28] Byte Enable Access Time 40 55 ns
Write Cycle
tWC Write Cycle Time 40 55 ns
tSCE[28] CE LOW to Write End 30 45 ns
tAW Address Valid to Write End 30 45 ns
Notes:
27.Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
28.To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
29.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
30.Test conditions used are Load 3.
31.This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform
1.8V
GND 90% 90%
10%
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1
3.0V/2.5V/1.8V
OUTPUT
R2
C = 30 pF
VTH = 0.8V
OUTPUT
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1
R2
3.0V/2.5V/1.8V
OUTPUT
RTH = 6 k
3 ns 3 ns
including scope and jig)
(Used for tLZ, tHZ, tHZWE, and tLZWE
3.0V/2.5V 1.8V
R1 102213500
R2 79210800
C = 30 pF
C = 5 pF
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