Contents
Main
1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,
Features
Selection Guide for VCC = 1.8V
Selection Guide for VCC = 2.5V
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,
Document #: 001-01638 Rev. *E Page 2 of 26
Figure 1. Top Level Block Diagram
Document #: 001-01638 Rev. *E Page 3 of 26
Pin Configurations
CYDC064B16 CYDC128B16 CYDC256B16
CYDC064B16, CYDC128B08, CYDC064B08
Pin Configurations
CYDC128B08
CYDC064B08
100-pin TQFP (Top View)
CYDC256B16, CYDC128B16,
Functional Description
Pin Definitions
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08
Architecture
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08
Maximum Ratings
Operating Range
Electrical Characteristics for VCC = 1.8V Over the Operating Range
Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range
Electrical Characteristics for VCC = 2.5V Over the Operating Range
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,
Electrical Characteristics for 3.0V
Capacitance
AC Test Loads and Waveforms
Switching Characteristics for VCC = 1.8V Over the Operating Range[27]
Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued)
Switching Characteristics for VCC = 2.5V Over the Operating Range
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08,
Switching Characteristics for VCC = 3.0V Over the Operating Range
Switching Characteristics for VCC = 2.5V Over the Operating Range (continued)
Switching Characteristics for VCC = 3.0V Over the Operating Range (continued)
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)
Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40]
Read Cycle No. 3 (Either Port)
Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46]
Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48]
Semaphore Read After Write Timing, Either Side
Timing Diagram of Semaphore Contention
Timing Diagram of Read with BUSY (M/S=HIGH)[53]
Write Timing with Busy Input (M/S = LOW)
Busy Timing Diagram No.1 (CE Arbitration)
CER Valid First
Right Address Valid First
Busy Timing Diagram No.2 (Address Arbitration)
CEL Valid First[54]
Interrupt Timing Diagrams
Right Side Sets INTL:
Right Side Clears INTR:
Left Side Sets INTR:
Ordering Information
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