Cypress CYDC064B08, CYDC064B16, CYDC128B08, CYDC128B16, CYDC256B16 CYDC064B16 CYDC128B16 CYDC256B16

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Document #: 001-01638 Rev. *E Page 3 of 26

Pin Configurations[3, 4, 5, 6, 7]

Notes:

3. A12L and A12R are NC pins for CYDC064B16.

4. IRR functionality is not supported for the CYDC256B16 device.

5. This pin is A13L for CYDC256B16 device.

6. This pin is A13R for CYDC256B16 device.

7. Leave this pin unconnected. No trace or power component can be connected to this pin.

100-Pin TQFP (Top View)

1

3

2

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

59

60

61

67

66

64

65

63

62

68

69

70

75

73

74

72

71

A4R

A5R

A6R

A7R

A8R

CER

A10R

INTR

A9R

VCC

A11R

NC[7]

VDDIOR

BUSYR

SEMR

A12R[3]

IRR1[6]

I/O15R

I/O14R

I/O13R

VSS

I/O12R

I/O11R

I/O10R

VSS

58

57

56

55

54

53

52

51

A4L

A5L

A6L

A7L

A8L

CEL

A10L

INTL

A9L

VCC

A11L

M/S

VDDIOL

BUSYL

SEML

A12L[3]

IRR0[5]

I/O0L

I/O1L

I/O2L

VSS

I/O3L

I/O4L

I/O5L

VSS

17

16

15

9

10

12

11

13

14

8

7

6

4

5

18

19

20

21

22

23

24

25

A3L

A2L

A1L

A0L

UBL

LBL

ODR0

R/WL

VSS

VSS

ODR2

VSS

R/WR

SFEN

OEL

ODR3

ODR4

OER

LBR

UBR

A0R

A1R

A2R

A3R

ODR1

34 35 36 424139 403837 43 44 45 5048 494746

I/O9R

I/O8R

VDDIOR

I/O7R

I/O6R

I/O5R

I/O1R

I/O4R

I/O2R

NC[7]

I/O15L

I/O12L

I/O11L

I/O3R

VSS

I/O14L

I/O13L

VSS

I/O10L

I/O9L

I/O8L

VDDIOL

I/O7L

I/O6L

I/O0R

3332313029282726

CYDC064B16CYDC128B16CYDC256B16

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Contents

Main 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Features Selection Guide for VCC = 1.8V Selection Guide for VCC = 2.5V CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Document #: 001-01638 Rev. *E Page 2 of 26 Figure 1. Top Level Block Diagram Document #: 001-01638 Rev. *E Page 3 of 26 Pin Configurations CYDC064B16 CYDC128B16 CYDC256B16 CYDC064B16, CYDC128B08, CYDC064B08 Pin Configurations CYDC128B08 CYDC064B08 100-pin TQFP (Top View) CYDC256B16, CYDC128B16, Functional Description Pin Definitions CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Architecture CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Maximum Ratings Operating Range Electrical Characteristics for VCC = 1.8V Over the Operating Range Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range Electrical Characteristics for VCC = 2.5V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Electrical Characteristics for 3.0V Capacitance AC Test Loads and Waveforms Switching Characteristics for VCC = 1.8V Over the Operating Range[27] Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued) Switching Characteristics for VCC = 2.5V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Switching Characteristics for VCC = 3.0V Over the Operating Range Switching Characteristics for VCC = 2.5V Over the Operating Range (continued) Switching Characteristics for VCC = 3.0V Over the Operating Range (continued) Switching Waveforms Read Cycle No.1 (Either Port Address Access) Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40] Read Cycle No. 3 (Either Port) Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46] Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48] Semaphore Read After Write Timing, Either Side Timing Diagram of Semaphore Contention Timing Diagram of Read with BUSY (M/S=HIGH)[53] Write Timing with Busy Input (M/S = LOW) Busy Timing Diagram No.1 (CE Arbitration) CER Valid First Right Address Valid First Busy Timing Diagram No.2 (Address Arbitration) CEL Valid First[54] Interrupt Timing Diagrams Right Side Sets INTL: Right Side Clears INTR: Left Side Sets INTR: Ordering Information Page Document History Page