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Cypress CYDC128B08, CYDC064B16, CYDC064B08 manual Pin Configurations 3, 4, 5, 6, Pin Tqfp Top View

Models: CYDC256B16 CYDC128B16 CYDC128B08 CYDC064B08 CYDC064B16

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Pin Configurations [3, 4, 5, 6, 7]

100-Pin TQFP (Top View)

A4L

A5L

A6L

A7L

A8L

CEL

SEML

INTL

BUSYL

A9L

A10L

VSS

VCC

A11L

A12L[3]

IRR0[5]

M/S

VDDIOL

I/O0L

I/O1L

I/O2L

VSS

I/O3L

I/O4L

I/O5L

	A		A		A		A		UB		LB		OE		R/W		SFEN		V		ODR0		ODR1		V		ODR2		ODR3		ODR4		V		R/W		OE		LB		UB		A		A		A		A
	3L		2L		1L		0L		L		L		L		L				SS						SS								SS		R		R		R		R		0R		1R		2R		3R



100 99					98		97		96		95		94		93		92	91			90	89			88		87	86		85		84			83		82		81		80		79		78		77		76
1																																																	75
2																																																	74
3																																																	73
4																																																	72
5																																																	71
6																																																	70
7																																																	69
8																																																	68
9																	CYDC064B16																																67
10																	CYDC064B16																																66
11																	CYDC128B16																																65
11																																																	65
12																	CYDC256B16																																64
13																	CYDC256B16																																63
14																																																	62
15																																																	61
16																																																	60
17																																																	59
18																																																	58
19																																																	57
20																																																	56
21																																																	55
22																																																	54
23																																																	53
24																																																	52
25																																																	51
26			27		28		29		30		31		32		33		34	35			36	37			38		39	40		41		42			43		44		45		46		47		48		49		50

A4R

A5R

A6R

A7R

A8R

CER

SEMR

INTR

BUSYR

A9R

A10R

VSS

VCC

A11R

A12R[3]

IRR1[6]

NC[7]

VDDIOR

I/O15R

I/O14R

I/O13R

VSS

I/O12R

I/O11R

I/O10R

6L

7L

DDIOL

8L

9L

10L

SS

11L

12L

13L

14L

15L

[7]

0R

1R

2R

3R

4R

SS

5R

6R

7R

DDIOR

8R

9R

I/O

I/O

V

I/O

I/O

I/O

V

I/O

I/O

I/O

I/O

I/O

NC

I/O

I/O

I/O

I/O

I/O

V

I/O

I/O

I/O

V

I/O

I/O

Notes:

3.A12L and A12R are NC pins for CYDC064B16.

4.IRR functionality is not supported for the CYDC256B16 device.

5.This pin is A13L for CYDC256B16 device.

6.This pin is A13R for CYDC256B16 device.

7.Leave this pin unconnected. No trace or power component can be connected to this pin.

Document #: 001-01638 Rev. *E

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Cypress CYDC128B08, CYDC064B16, CYDC064B08, CYDC256B16, CYDC128B16 manual Pin Configurations 3, 4, 5, 6, Pin Tqfp Top View

Contents

Unit FeaturesSelection Guide for VCC = CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 CYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6 CYDC064B08 Pin Configurations 7, 8, 9 Functional Description Pin Definitions Input Read Register InterruptsBusy Master/Slave Architecture Semaphore Operation Example Function 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Input Read Register Operation16 Operating Range Electrical Characteristics for V CC =Range Ambient Temperature Maximum Ratings23 Standb y Cur rent One Port Cmos Ind Input Leakage Current Input LOW Voltage 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input High Voltage 5V any port Parameter Description Test Conditions Max Unit Capacitance Write Cycle AC7Test Loads and Waveforms Busy Timing Interrupt TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No Either Port36, 38, 41 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No.2 Either Port CE/OE Access36, 39 Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51 Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53 Busy Timing Diagram No.1 CE Arbitration CEL Valid First54 CER Valid FirstRight Address Valid First Left Side Clears INT L Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Right Side Sets Intl Ordering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package Diagram Document History Issue Date Orig. Description of Change