Cypress Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued)

CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E Page 14 of 26
tHA Address Hold From Write End 0 0 ns
tSA[28] Address Set-up to Write Start 0 0 ns
tPWE Write Pulse Width 25 40 ns
tSD Data Set-up to Write End 20 30 ns
tHD Data Hold From Write End 0 0 ns
tHZWE[30, 31] R/W LOW to High Z 15 25 ns
tLZWE[30, 31] R/W HIGH to Low Z 0 0 ns
tWDD[32] Write Pulse to Data Delay 55 80 ns
tDDD[32] Write Data Valid to Read Data Valid 55 80 ns
Busy Timing[33]
tBLA BUSY LOW from Address Match 30 45 ns
tBHA BUSY HIGH from Address Mismatch 30 45 ns
tBLC BUSY LOW from CE LOW 30 45 ns
tBHC BUSY HIGH from CE HIGH 30 45 ns
tPS[34] Port Set-up for Priority 5 5 ns
tWB R/W HIGH after BUSY (Slave) 0 0 ns
tWH R/W HIGH after BUSY HIGH (Slave) 20 35 ns
tBDD[35] BUSY HIGH to Data Valid 30 40 ns
Interrupt Timing[33]
tINS INT Set Time 35 45 ns
tINR INT Reset Time 35 45 ns
Semaphore Timing
tSOP SEM Flag Update Pulse (OE or SEM)10 15 ns
tSWRD SEM Flag Write to Read Time 10 10 ns
tSPS SEM Flag Contention Window 10 10 ns
tSAA SEM Address Access Time 40 55 ns
Notes:
32.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
33.Test conditions used are Load 2.
34.Add 2ns to this value when the I/O ports are operating at different voltages.
35.tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued)
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
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