CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E Page 15 of 26
Switching Characteristics for VCC = 2.5V Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 40 55 ns
tAA Address to Data Valid 40 55 ns
tOHA Output Hold From Address Change 5 5 ns
tACE[28] CE LOW to Data Valid 40 55 ns
tDOE OE LOW to Data Valid 25 30 ns
tLZOE[29, 30, 31] OE Low to Low Z 2 2 ns
tHZOE[29, 30, 31] OE HIGH to High Z 15 15 ns
tLZCE[29, 30, 31] CE LOW to Low Z 2 2 ns
tHZCE[29, 30, 31] CE HIGH to High Z 15 15 ns
tPU[31] CE LOW to Power-Up 0 0 ns
tPD[31] CE HIGH to Power-Down 40 55 ns
tABE[28] Byte Enable Access Time 40 55 ns
Write Cycle
tWC Write Cycle Time 40 55 ns
tSCE[28] CE LOW to Write End 30 45 ns
tAW Address Valid to Write End 30 45 ns
tHA Address Hold From Write End 0 0 ns
tSA[28] Address Set-up to Write Start 0 0 ns
tPWE Write Pulse Width 25 40 ns
tSD Data Set-up to Write End 20 30 ns
tHD Data Hold From Write End 0 0 ns
tHZWE[30, 31] R/W LOW to High Z 15 25 ns
tLZWE[30, 31] R/W HIGH to Low Z 0 0 ns
tWDD[32] Write Pulse to Data Delay 55 80 ns
tDDD[32] Write Data Valid to Read Data Valid 55 80 ns
Busy Timing[33]
tBLA BUSY LOW from Address Match 30 45 ns
tBHA BUSY HIGH from Address Mismatch 30 45 ns
tBLC BUSY LOW from CE LOW 30 45 ns
tBHC BUSY HIGH from CE HIGH 30 45 ns
tPS[34] Port Set-up for Priority 5 5 ns
tWB R/W HIGH after BUSY (Slave) 0 0 ns
tWH R/W HIGH after BUSY HIGH (Slave) 20 35 ns
tBDD[35] BUSY HIGH to Data Valid 30 40 ns
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